Specifications ispGDX80VA
External Timing Parameters
Over Recommended Operating Conditions
-9
-7
TEST1
PARAMETER COND.
UNITS
#
DESCRIPTION
MIN. MAX.
MIN. MAX.
tpd2
A
A
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
A
A
A
A
B
C
B
C
–
–
–
–
D
A
1 Data Prop. Delay from Any I/O pin to Any I/O Pin (4:1 MUX)
2 Data Prop. Delay from MUXsel Inputs to Any Output (4:1 MUX)
–
–
7.0
7.0
–
–
–
9.0
9.0
–
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsel2
83
62.5
7.0
6.0
7.0
6.0
4.0
3.0
8.5
0.0
3.0
0.0
3.0
0.0
3.0
0.0
–
fmax (Tog.)
fmax (Ext.)
tsu1
tsu2
tsu3
3 Clock Frequency, Max. Toggle
100
80
5.5
4.5
5.5
4.5
3.5
2.5
6.5
0.0
2.5
0.0
2.5
0.0
2.5
0.0
–
1
(
)
–
4 Clock Frequency with External Feedback
–
tsu3+tgco1
–
5 Input Latch or Register Setup Time Before Yx
–
–
6 Input Latch or Register Setup Time Before I/O Clock
7 Output Latch or Register Setup Time Before Yx
8 Output Latch or Register Setup Time Before I/O Clock
9 Global Clock Enable Setup Time Before Yx
10 Global Clock Enable Setup Time Before I/O Clock
11 I/O Clock Enable Setup Time Before Yx
12 Input Latch or Reg. Hold Time (Yx)
–
–
–
–
tsu4
–
–
tsuce1
tsuce2
tsuce3
th1
th2
th3
–
–
–
–
–
–
–
–
13 Input Latch or Reg. Hold Time (I/O Clock)
14 Output Latch or Reg. Hold Time (Yx)
15 Output Latch or Reg. Hold Time (I/O Clock)
16 Global Clock Enable Hold Time (Yx)
–
–
–
–
th4
–
–
thce1
thce2
thce3
tgco12
tgco22
tco12
tco22
ten2
–
–
17 Global Clock Enable Hold Time (I/O Clock)
18 I/O Clock Enable Hold Time (Yx)
–
–
–
9.0
13.5
11.5
15.7
10.5
10.5
10.5
10.5
–
19 Output Latch or Reg. Clock (from Yx) to Output Delay
20 Input Latch or Register Clock (from Yx) to Output Delay
21 Output Latch or Register Clock (from I/O pin) to Output Delay
22 Input Latch or Register Clock (from I/O pin) to Output Delay
23 Input to Output Enable
7.0
11.0
9.0
13.0
8.5
8.5
8.5
8.5
–
–
–
–
–
–
–
–
–
tdis2
24 Input to Output Disable
–
–
ttoeen2
ttoedis2
twh
25 Test OE Output Enable
–
–
–
26 Test OE Output Disable
–
6.0
6.0
–
27 Clock Pulse Duration, High
5.0
5.0
–
–
twl
trst
trw
tsl
28 Clock Pulse Duration, Low
–
22.0
–
29 Register Reset Delay from RESET Low
30 Reset Pulse Width
18.0
–
18.0
–
14.0
–
9.0
1.0
31 Output Delay Adder for Output Timings Using Slow Slew Rate
32 Output Skew (tgco1 Across Chip)
7.0
0.5
–
tsk
–
1. All timings measured with one output switching, fast output slew rate setting, except tsl.
2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is
used as I/O voltage reference.
12