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5512VA 参数 Datasheet PDF下载

5512VA图片预览
型号: 5512VA
PDF下载: 下载PDF文件 查看货源
内容描述: 在系统可编程3.3V SuperWIDE⑩高密度PLD [In-System Programmable 3.3V SuperWIDE⑩ High Density PLD]
分类和应用:
文件页数/大小: 26 页 / 331 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Specifications ispLSI 5512VA  
External Switching Characteristics  
Over Recommended Operating Conditions  
TEST3  
COND.  
-110  
-100  
-70  
DESCRIPTION 4,5  
UNITS  
PARAM.  
#
MIN. MAX. MIN. MAX. MIN. MAX.  
6
A
A
1 Data Prop. Delay, 5PT Bypass  
110  
91  
143  
6
8.5  
10  
4
100  
69  
125  
8
10  
13  
5.5  
70  
45  
83  
12  
0
15  
19  
8
ns  
ns  
t
t
f
f
f
t
t
t
t
t
pd1  
6
2 Data Propagation Delay  
pd2  
A
3 Clock Frequency with Internal Feedback1  
4 Clock Freq. with Ext. Feedback,1/(tsu2 + tco1)  
5 Clock Frequency, Max Toggle2  
MHz  
MHz  
MHz  
ns  
max  
A
max (Ext.)  
max (Tog.)  
su1  
6 GLB Reg. Setup Time before Clk, 5PT bypass  
7 GLB Reg. Clock to Output Delay  
6
0
0
ns  
co1  
8 GLB Reg. Hold Time after Clock, 5PT bypass  
9 GLB Reg. Setup Time before Clock  
10 GLB Reg. Hold Time after Clock  
ns  
h1  
7
9
14  
0
ns  
su2  
h2  
0
0
ns  
GLB Reg. Setup Time before Clock, Input Reg.  
Path (CLK0/1)  
11  
4.5  
3.5  
0
6
5
0
0
9
7
0
0
ns  
ns  
ns  
ns  
tsu3 (CLK0/1)  
tsu3 (CLK2/3)  
th3 (CLK0/1)  
th3 (CLK2/3)  
GLB Reg. Setup Time before Clock, Input Reg.  
Path (CLK2/3)  
12  
GLB Reg. Hold Time after Clock, Input Reg. Path  
(CLK0/1)  
13  
GLB Reg. Hold Time after Clock, Input Reg. Path  
(CLK2/3)  
14  
0
A
15 Ext. Reset Pin to Output Delay  
16 Ext. Reset Pulse Duration  
7.5  
17  
9
20  
12  
24  
8
14  
6
30  
18  
30  
12  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t
t
t
t
t
t
t
r1  
rw1  
B/C 17 Local Product Term Output Enable/Disable  
B/C 18 Global Product Term Output Enable/Disable  
B/C 19 Global OE Input to Output Enable/Disable  
10  
20  
6.5  
4
ptoe/dis  
gptoe/dis  
goe/dis  
wh  
20 Ext. Sync. Clock Pulse Duration, High  
21 Ext. Sync. Clock Pulse Duration, Low  
3.5  
3.5  
4
6
wl  
1. Standard 32-bit counter using GRP feedback.  
2. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.  
3. Reference Switching Test Conditions section.  
4. Unless noted otherwise, all timing numbers are taken with worst case PTSA fanout, a GRP load of 1 GLB, and CLK0.  
5. Timing parameters measured using normal active output driver.  
6. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is  
used as I/O voltage reference.  
Timing Ext.5512VA/4.0.eps  
13