Specifications ispLSI 5256V
Figure 4. ispLSI 5000V Macrocell
VCCIO
VCC
VCCIO
Global PTOE 0
Global PTOE 1
Global PTOE 2
Global PTOE 3
Global PTOE 4
Global PTOE 5
PTOE
GOE0
GOE1
TOE
PTSA bypass
I/O Pad
Delay
D
Q
PTSA
D/T
Slew Open
rate drain
Shared PT Clock 0
Shared PT Clock 1
2.5V/3.3V
Output
Clk En
PT Clock
PT Reset
To GRP
R/L
P
CLK0
CLK1
CLK2
CLK3
Clk
R
D
D
Q
Q
SET/RESET
D/T
Clk En
Clk
Register/
Latch
Shared PT (P)reset 0
Shared PT (P)reset 1
PT Preset
Programmable
Speed/Power
Option
R
P
6