Specifications
ispLSI 5256V
ispLSI 5000V Description (Continued)
sharing up to a maximum of 35 product terms for a single
function. Alternatively, the PTSA can be bypassed for
functions of five product terms or less. The five extra
product terms are used for shared GLB controls, set,
reset, clock, clock enable and output enable.
The 32 registered macrocells in the GLB are driven by the
32 outputs from the PTSA or the PTSA bypass. Each
macrocell contains a programmable XOR gate, a pro-
grammable register/latch/toggle flip-flop and the
necessary clocks and control logic to allow combinatorial
or registered operation. The macrocells each have two
outputs, which can be fed back through the Global
Routing Pool. This dual output capability from the
macrocell allows efficient use of the hardware resources.
One output can be a registered function for example,
while the other output can be an unrelated combinatorial
function. A direct register input from the I/O pad facili-
tates efficient use of this feature to construct high-speed
input registers.
Macrocell registers can be clocked from one of several
global or product term clocks available on the device. A
global and product term clock enable is also provided,
eliminating the need to gate the clock to the macrocell
registers. Reset and preset for the macrocell register is
provided from both global and product term signals. The
macrocell register can be programmed to operate as a D-
type register, a D-type latch or a T-type flip flop.
The 32 outputs from the GLB can drive both the Global
Routing Pool and the device I/O cells. The Global
Routing Pool contains one line from each macrocell
output and one line from each I/O pin.
The input buffer threshold has programmable TTL/3.3V/
2.5V compatible levels. The output driver can source
4mA and sink 8mA. The output drivers have a separate
VCCIO reference input which is independent of the main
VCC supply for the device. This feature allows the output
Table 1. ispLSI 5000V Family
drivers to drive either 3.3V or 2.5V output levels while the
device logic and the output current drive is always pow-
ered from 3.3V. The output drivers also provide individually
programmable edge rates and open drain capability. A
programmable pullup resistor is provided to tie off un-
used inputs and a programmable bus-hold latch is
available to hold tristate outputs in their last valid state
until the bus is driven again by some device.
The ispLSI 5000V Family features 3.3V, non-volatile in-
system programmability for both the logic and the
interconnect structures, providing the means to develop
truly reconfigurable systems. Programming is achieved
through the industry standard IEEE 1149.1-compliant
Boundary Scan interface. Boundary Scan test is also
supported through the same interface.
An enhanced, multiple cell security scheme is provided
that prevents reading of the JEDEC programming file
when secured. After the device has been secured using
this mechanism, the only way to clear the security is to
execute a bulk-erase instruction.
ispLSI 5000V Family Members
The ispLSI 5000V family ranges from 256 macrocells to
512 macrocells and operates from a 3.3V power supply.
All family members will be available with multiple pack-
age options. The ispLSI 5000V family device matrix
showing the various bondout options is shown in the table
below.
The interconnect structure (GRP) is very similar to Lattice's
existing 1000, 2000 and 3000 families, but with an
enhanced interconnect structure for optimal pin locking
and logic routing. The ispLSI 5000V family does not,
however, use registered I/O cells or an Output Routing
Pool.
Package Type
Device
ispLSI 5256V
ispLSI 5384V
ispLSI 5512V
GLBs
8
12
16
Macrocells
256
384
512
208 BGA*
144 I/O
144 I/O
—
208 PQFP
144 I/O
144 I/O
—
272 BGA
192 I/O
192 I/O
—
388 BGA
—
288 I/O
288 I/O
*1.0mm ball pitch Fine Pitch BGA
3
LATTICE [ LATTICE SEMICONDUCTOR ]
