Specifications ispLSI 2032VE
Power Consumption
Power consumption in the ispLSI 2032VE device de- used. Figure 3 shows the relationship between power
pends on two primary factors: the speed at which the and operating speed.
device is operating and the number of product terms
Figure 3. Typical Device Power Consumption vs fmax
150
125
ispLSI 2032VE-225
100
75
ispLSI 2032VE-180
and slower
50
25
50
0
25
75
100
125
150
175
200
225
fmax (MHz)
Notes: Configuration of two 16-bit counters
Typical current at 3.3V, 25° C
I
can be estimated for the ispLSI 2032VE using the following equation:
CC
For ispLSI 2032VE-225: I (mA) = 4.5 + (# of PTs 1.29) + (# of nets Max freq 0.0068)
*
*
*
CC
For ispLSI 2032VE-180 and slower: I (mA) = 4.5 + (# of PTs 1.05) + (# of nets Max freq 0.0068)
*
*
*
CC
Where:
# of PTs = Number of product terms used in design
# of nets = Number of signals used in device
Max freq = Highest clock frequency to the device (in MHz)
The I
estimate is based on typical conditions (V = 3.3V, room temperature) and an assumption of two
CC
CC
GLB loads on average exists. These values are for estimates only. Since the value of I
operating conditions and the program in the device, the actual I
CC
is sensitive to
CC
should be verified.
0127A/2032VE
10
LATTICE [ LATTICE SEMICONDUCTOR ]
