16 | Keysight | N4960A Serial BERT 17 and 32 Gb/s - Data Sheet
N4960A clock source/BERT controller specifications
Configuration
Frequency synthesizer with three differential outputs: Jitter, Delay, and Divided. Clock generator Jitter
and Delay clocks are shared with the remote head port connectors. Changing the controller clock output
parameters while pattern generator and/or error detector remote heads are operating will effect their
operation. Pattern generator and error detector remote heads operate with a half-rate clock - therefore
the remote head Data rate will be double the frequency of the controller Clock.
1 to 16 GHz with no remote heads connected
Frequency
2 to 8.5 GHz when one or two 17 Gb/s remote heads are connected
2.5 to 16 GHz when one or two 32 Gb/s remote heads are connected
1 kHz (front panel)
Frequency resolution
Outputs
Jitter (stressed), Delay, and Divided (non-stressed)
Output configuration (all outputs)
Differential, with amplitude, offset and termination voltage adjustment (can be used single-ended
without terminating unused outputs)
Amplitude range
Offset range
300 mV to 1.7 V (p-p), single-ended
–2.4 to +2.4 V (limited by termination voltage, see Figure 24)
On divided clock output, this is only valid when the divide ratio is a power of 2.
–2.4 to +2.4 V (limited by offset voltage, see Figure 24)
< 23 ps typical
< 700 fs rms typical from 2 to 16 GHz
Termination voltage range
Rise time (20% to 80%)
Intrinsic jitter
Duty cycle
Jitter and delay outputs
Divided output
50% ±5%
50% ±5% at divide ratios which are a power of 2
Duty cycle varies between 33 and 66% at divide ratios which are not a power of 2
50% ±10% when divide ratio is set to 1 for amplitudes ≥ 500 mV
± 1 ppm typical, ± 5 ppm maximum
Frequency accuracy
Reference frequency
External clock
Maximum clock input amplitude
Clock input sensitivity
External delayed clock input
10.0 MHz, single-ended output and input on rear panel
Single-ended input can be substituted for internal synthesizer, drives all clocks
2 V (p-p)
200 mV typical
Single-ended input drives Delay clock outputs only
Maximum delayed clock input amplitude
Delayed clock input sensitivity
Spread spectrum clock (N4960A-CJ1 serial
BERT controller only)
2 V (p-p)
150 mV typical
Phase deviation appears on all outputs (internal synthesizer only)
Deviation range
0 to 1.0% (10,000 ppm)
Modulation frequency range
Modulation wave shape
1 Hz to 50 kHz
Triangle
Deviation direction
Down spread, center spread, or up spread
Divided clock divide ratio
÷ 1, 2, 3,…, 99,999,999, with no missing integers (waveshape of divided clock slower than
≈1 MHz will be differentiated)
0 to ±1,000 UI
1 mUI
Delayed clock delay range
Delayed clock delay resolution
Connector type
All signals except 10 MHz ref in/out
10 MHz ref in, out
SMA
BNC
Offset voltage vs termination voltage
2.0
1.0
Valid settings of offset and termination voltages
0.0
–1.0
–2.0
–2.0
–1.0
0.0
1.0
2.0
Termination voltage (V)
Figure 24. Maximum offset and termination voltage ranges.
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