12 | Keysight | N4960A Serial BERT 17 and 32 Gb/s - Data Sheet
Typical applications
100G ethernet
accomplished using four 32 Gb/s pattern
This configuration supports asychro-
nous clocking on all 4 lanes, which is
required for characterizing 100GE-SR4
system components.
The 100G Ethernet is the next generation
25 Gb/s standard for evaluating chip-to-
chip and chip-to-module electrical com-
munication links within optical networks.
generators (N4951A-P32 or N4951B-
H32/-D32) to the input of the optical
module. The optical module is tested in
loopback mode with the receiver’s elec-
trical outputs connected to four 32 Gb/s
error detectors.
The example configuration below (Figure
19) requires four 25 Gb/s lanes. This is
N4960A
controller
N4951A-P32
pattern generator
N4951A-P32
pattern generator
Divided clk out
Optical module
4 x 25 Gb/s
N4951A-P32
Vertical
cavity
surface
emitting
lasers
25 Gb/s
Clk in
pattern generator
25 Gb/s
25 Gb/s
25 Gb/s
Laser
drivers
N4960A
controller
N4951A-P32
pattern generator
MMF
4 x 25 Gb/s
Clk in
25 Gb/s
25 Gb/s
25 Gb/s
25 Gb/s
N4952A-E32
error detector
Clock
Trans
PIN
N4960A
controller
data
impedance
photodiodes
amplifiers
recover
N4952A-E32
error detector
N4952A-E32
error detector
Clk in
100 GE-SR4
optical
interface
CAUI2
N4960A
controller
electrical
N4952A-E32
error detector
interferface
Figure 19. Test setup for 100G ethernet.
Fast SerDes design in FPGA and other communication ICs
SerDes circuits are often integrated into the SerDes. The BER and jitter tolerance can
streams for the specific application. In
addition, the software simplifies the
task of setting up and running BER and
jitter tolerance tests.
design of FPGAs, ASICs, and other commu-
nication ICs. To ensure successful integra-
tion, SerDes circuits must be fully tested
and characterized before integration.
be measured at all rates up to 32 Gb/s
using the N4960A serial BERT on the
transmit side of a SerDes.
The pattern editor in the N4980A multi-in-
strument BERT software enables the
design of stress patterns and pattern
Figure 18 shows a configuration for testing
the received data through a loopback in a
Rx
N4951A-P32
pattern generator
DUT
N4960A
controller
N4952A-E32
Tx
error detector
Figure 20. Test setup for communication ICs.
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