07 | Keysight | M3102A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Data acquisition blocks (DAQs) specifications
M3102A-CH2
M3102A-CH4
Typ
Parameter
Min
Typ
2
Max
Min
Max Units
Comments
General specifications
DAQs
4
5
1 per channel
Aggregated speed
Acquisition burst multiple
Acquisition RAM capacity
Acquisition RAM capacity effic.
Trigger
1000
2000 MSa/s
For all onboard DAQs combined
5
Samples Burst length must be a multiple of this value
957M Samples Maximum depends on onboard RAM
15
957M
15
93.5
93.5
%
Effic. = waveform size / waveform size in RAM
Selec.
Selec.
Hardware trigger (analog channels, input trigger,
backplane triggers), software trigger
DAQ specifications
Speed
500
500 MSa/s
Bits
Per DAQ
Resolution
14
14
Table 3. Data acquisition blocks (DAQs) specifications
Clock system specifications
M3102A
Parameter
Min
Max
Units
Comments
General specifications
Clock frequency (-CLF)
Clock frequency (-CLV)
500
100
500
500
MHz
MHz
Fixed clock
Variable clock
Table 4. Clock system specifications
System specifications
Environmental specifications (PXI Express)
M3102A-CH2
M3102A-CH4
Typ
Parameter
Min
Typ
Max
Min
Max Units
Comments
System bus
Slots
1
1
Slot
PXI Express (CompactPCI Express compatible)
Automatic gen negotiation, chassis dependent
Automatic lane negotiation, chassis dependent
PCI Express type
PCI Express link
Power dissipation
3.3V PXIe power supply
12V PXIe power supply
Gen 1
1
Gen 2 Gen 1
Gen 2
4
–
4
1
Lanes
1.5
2
1.5
2
A
A
~ 5 W
~ 24 W
Table 5. Environmental specifications (PXI Express)
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