06 | Keysight | M3102A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
I/O specifications
Analog input characteristics
Number of channels
Sampling rate
CH2 or CH4
500 MSa/s option CLF (Table 4)
variable rate option CLV (Table 4)
Configurable inputs: impedance
Configurable inputs: Coupling
Input voltage range (50Ω)
Input voltage range (HiZ)
50Ω or 1MΩ (HiZ)
AC or DC
125 mVpp to 8Vpp (7 scales: 0.125, 0.25, 0,5, 1, 2, 4, 8 Vpp)
200 mVpp to 16Vpp (7 scales: 0.2, 0.4, 0.8, 2, 4, 8, 16 Vpp)
200 MHz
Bandwidth limit filters
Effective number of bits (ENOB)1
Noise floor1
10.6 bits @ 95 MHz (typical)
-146 dBm/Hz
SINAD1
66 dB @ 95 MHz (typical)
Spurious free dynamic range (SFDR) + Total Harmonic Distorsion1
71 dBc @ 95 MHz (typical)
1. Measured at -1 DBFS input signal with 1 Vpp 50Ω
Table 2a.
M3102A
Parameter
Min
Typ
Max
Units
Comments
Reference clock output
Frequency
10 to 12.52
MHz
mVpp
dBm
Ω
Generated from the internal clock. User selectable
Voltage
800
2
On a 50 Ω load
On a 50 Ω load
AC coupled
Power
Source impedance
50
External I/O trigger/marker
VIH
2
0
5
V
VIL
0.8
3.3
0.25
V
VOH
2.4
0
V
On a high Z load
On a high Z load
VOL
V
Input impedance
Source impedance
Speed
10
K Ω
–
TTL
100
MHz
2.
CLF option is set to 10 MHz while with CLV option varies from 12.5 MHz to 10 MHz
Table 2b.
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