04 | Keysight | M3102A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Functional block diagram
Channel 1
Channel 1
output
Channel x
Input settings
Full scale, ꢀ,
coupling (as
available)
Prescaler
ꢁ
Data
acquisition
(DAQx)
Channel x
output
Analog
trigger
Channel n
Channel n
output
Figure 1. M3102A input functional block diagram, all channels have identical input structure
Ordering information
Product
Description
M3102A
PXIe digitizer: 500 MSa/s, 14 Bits
Options
Description
M3102A-CH2 / -CH4
M3102A-CLV / -CLF
M3102A-M01 / -M12 / -M20
HW programming options
M3102A-HVI
Two channels / four channels
Variable sampling clock / fixed sampling clock, low jitter
Memory 16 MB, 8 MSamples / 128 MB, 60 MSamples / 2 GB, 1 GSamples
Description
Enabled HVI programming, requires an HVI design environment license (M3601A)
Enabled FPGA programming, requires -K32 or -K41 option and an FPGA design environment license (M3602A)
FPGA, Xilinx 7K325T / 7K410T, required for -FP1 option only (needs memory option -M20)
M3102A-FP1
M3102A-K32 / -K41
All options must be selected at time of purchase and are not upgradable
These options represent the standard configuration
Related software
M3601A
Description
HVI design environment
FPGA design environment
M3602A