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IS42S32400B-6BL 参数 Datasheet PDF下载

IS42S32400B-6BL图片预览
型号: IS42S32400B-6BL
PDF下载: 下载PDF文件 查看货源
内容描述: 4Meg ×32 128兆位同步DRAM [4Meg x 32 128-MBIT SYNCHRONOUS DRAM]
分类和应用: 存储内存集成电路动态存储器时钟
文件页数/大小: 60 页 / 625 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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®
IS42S32400B  
ISSI  
Initialization  
FUNCTIONAL DESCRIPTION  
SDRAMs must be powered up and initialized in a  
predefinedmanner.  
The128MbSDRAMsarequad-bankDRAMswhichoperate  
at3.3Vandincludeasynchronousinterface(allsignalsare  
registered on the positive edge of the clock signal, CLK).  
Each of the 33,554,432-bit banks is organized as 4,096  
rows by 256 columns by 32 bits.  
The128MSDRAMisinitializedafterthepowerisappliedto  
VDD and VDDQ (simultaneously) and the clock is stable with  
DQM High and CKE High.  
Read and write accesses to the SDRAM are burst oriented;  
accesses start at a selected location and continue for a  
programmed number of locations in a programmed  
sequence. Accesses begin with the registration of an AC-  
TIVEcommandwhichisthenfollowedbyaREADorWRITE  
command. The address bits registered coincident with the  
ACTIVE command are used to select the bank and row to  
A 100µs delay is required prior to issuing any command  
other than a COMMAND INHIBIT or aNOP. The COMMAND  
INHIBITorNOPmaybeappliedduringthe100µsperiodand  
should continue at least through the end of the period.  
With at least one COMMAND INHIBIT or NOP command  
havingbeenapplied,aPRECHARGEcommandshouldbe  
appliedoncethe100µsdelayhasbeensatisfied. Allbanks  
mustbeprecharged. Thiswillleaveallbanksinanidlestate  
after which at least two AUTO REFRESH cycles must be  
performed. After the AUTO REFRESH cycles are complete,  
the SDRAM is then ready for mode register programming.  
beaccessed(BA0andBA1selectthebank,A0-A11selecttherow)  
.
The address bits A0-A7 registered coincident with the READ  
orWRITEcommandareusedtoselectthestartingcolumn  
location for the burst access.  
Prior to normal operation, the SDRAM must be initialized.  
The following sections provide detailed information covering  
device initialization, register definition, command  
descriptions and device operation.  
The mode register should be loaded prior to applying any  
operational command because it will power up in an un-  
known state.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
19  
PRELIMINARYINFORMATION Rev. 00G  
06/15/06