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IS42S32400B-6BL 参数 Datasheet PDF下载

IS42S32400B-6BL图片预览
型号: IS42S32400B-6BL
PDF下载: 下载PDF文件 查看货源
内容描述: 4Meg ×32 128兆位同步DRAM [4Meg x 32 128-MBIT SYNCHRONOUS DRAM]
分类和应用: 存储内存集成电路动态存储器时钟
文件页数/大小: 60 页 / 625 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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®
IS42S32400B  
ISSI  
(1,2,3)  
AC ELECTRICAL CHARACTERISTICS  
-6  
-7  
Symbol Parameter  
Min.  
Max.  
Min.  
Max.  
Units  
tCK3  
tCK2  
Clock Cycle Time  
CAS Latency = 3  
CAS Latency = 2  
6
8
7
10  
ns  
ns  
tAC3  
tAC2  
Access Time From CLK  
CAS Latency = 3  
CAS Latency = 2  
5.4  
6.5  
5.4  
6.5  
ns  
ns  
tCHI  
tCL  
CLK HIGH Level Width  
CLK LOW Level Width  
Output Data Hold Time  
2.5  
2.5  
2.5  
2.5  
ns  
ns  
tOH3  
tOH2  
CAS Latency = 3  
CAS Latency = 2  
2.7  
2.7  
2.7  
3
ns  
ns  
tLZ  
Output LOW Impedance Time  
Output HIGH Impedance Time  
Input Data Setup Time(2)  
Input Data Hold Time(2)  
Address Setup Time(2)  
Address Hold Time(2)  
CKE Setup Time(2)  
CKE Hold Time(2)  
Command Setup Time (CS, RAS, CAS, WE, DQM)(2)  
Command Hold Time (CS, RAS, CAS, WE, DQM)(2)  
Command Period (REF to REF / ACT to ACT)  
Command Period (ACT to PRE)  
0
5.4  
0
2.7  
1.5  
0.8  
1.5  
0.8  
1.5  
0.8  
1.5  
0.8  
67.5  
45  
5.4  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tHZ  
2.7  
1.5  
0.8  
1.5  
0.8  
1.5  
0.8  
1.5  
0.8  
60  
tDS  
tDH  
tAS  
tAH  
tCKS  
tCKH  
tCS  
tCH  
tRC  
tRAS  
tRP  
42  
100K  
100K  
Command Period (PRE to ACT)  
18  
20  
tRCD  
tRRD  
tDPL  
Active Command To Read / Write Command Delay Time  
Command Period (ACT [0] to ACT[1])  
18  
20  
12  
14  
Input Data To Precharge  
Command Delay time  
12  
14  
tDAL  
Input Data To Active / Refresh  
30  
34  
ns  
Command Delay time (During Auto-Precharge)  
tMRD  
tDDE  
tXSR  
tT  
Mode Register Program Time  
Power Down Exit Setup Time  
Self-Refresh Exit Time  
12  
6
10  
64  
15  
7.5  
70  
1
10  
64  
ns  
ns  
ns  
ns  
ms  
70  
1
Transition Time  
tREF  
Refresh Cycle Time (4096)  
Notes:  
1. The power-on sequence must be executed before starting memory operation.  
2. Measured with tT = 1 ns. If clock rising time is longer than 1ns, (tR /2 - 0.5) ns should be added to the parameter.  
3. Thereferencelevelis1.4Vwhenmeasuringinputsignaltiming. RiseandfalltimesaremeasuredbetweenVIH(min.)andVIL (max).  
16  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
PRELIMINARY INFORMATION Rev. 00G  
06/15/06