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IC43R16320B-6TL 参数 Datasheet PDF下载

IC43R16320B-6TL图片预览
型号: IC43R16320B-6TL
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX16, 0.7ns, CMOS, PDSO66, ROHS COMPLIANT, PLASTIC, TSOP2-66]
分类和应用: 动态存储器双倍数据速率光电二极管内存集成电路
文件页数/大小: 48 页 / 839 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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IS43R16320B  
IC43R16320B  
Current state  
/CS  
H
/RAS /CAS /WE Address  
Command  
DESL  
Operation  
NOP  
Next state  
Write with auto-  
pre-charge*10  
×
×
×
×
Precharging  
L
L
L
L
L
L
L
H
H
H
H
L
H
H
L
H
L
×
NOP  
NOP  
Precharging  
×
BST  
ILLEGAL  
H
L
BA, CA, A10  
BA, CA, A10  
BA, RA  
BA, A10  
×
READ/READA  
WRIT/WRIT A  
ACT  
ILLEGAL*14  
ILLEGAL*14  
ILLEGAL*11, 14  
ILLEGAL*11, 14  
ILLEGAL  
L
H
H
L
H
L
L
PRE, PALL  
L
×
Remark: H: VIH. L: VIL. ×: VIH or VIL  
Notes: 1. The DDR SDRAM is in "Precharging" state for tRP after precharge command is issued.  
2. The DDR SDRAM reaches "IDLE" state tRP after precharge command is issued.  
3. The DDR SDRAM is in "Refresh" state for tRFC after auto-refresh command is issued.  
4. The DDR SDRAM is in "Activating" state for tRCD after ACT command is issued.  
5. The DDR SDRAM is in "Active" state after "Activating" is completed.  
6. The DDR SDRAM is in "READ" state until burst data have been output and DQ output circuits are turned  
off.  
7. The DDR SDRAM is in "READ with auto-precharge" from READA command until burst data has been  
output and DQ output circuits are turned off.  
8. The DDR SDRAM is in "WRITE" state from WRIT command to the last burst data are input.  
9. The DDR SDRAM is in "Write recovering" for tWR after the last data are input.  
10. The DDR SDRAM is in "Write with auto-precharge" until tWR after the last data has been input.  
11. This command may be issued for other banks, depending on the state of the banks.  
12. All banks must be in "IDLE".  
13. Before executing a write command to stop the preceding burst read operation, BST command must be  
issued.  
14. The DDR SDRAM supports the concurrent auto-precharge feature, a read with auto-precharge enabled,or  
a write with auto-precharge enabled, may be followed by any column command to other banks, as long as  
that command does not interrupt the read or write data transfer, and all other related limitations apply.  
(E.g. Conflict between READ data and WRITE data must be avoided.)  
The minimum delay from a read or write command with auto precharge enabled, to a command to a  
different bank, is summarized below.  
To command (different bank, non-  
interrupting command)  
Minimum delay  
(Concurrent AP supported)  
From command  
Read w/AP  
Units  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
Read or Read w/AP  
Write or Write w/AP  
Precharge or Activate  
Read or Read w/AP  
Write or Write w/AP  
Precharge or Activate  
BL/2  
CL(rounded up)+ (BL/2)  
1
Write w/AP  
1 + (BL/2) + tWTR  
BL/2  
1
18  
Integrated Silicon Solution, Inc. — www.issi.com  
Rev. 00B  
06/11/08  
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