IS42S81600D, IS42S16800D
PIN CONFIGURATION
54-ball fBGA for x16 (Top View) (8.00 mm x 13.00 mm Body, 0.8 mm Ball Pitch)
PACKAGE CODE:
B
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
VSS DQ15 VSSQ
DQ14 DQ13 VDDQ
DQ12 DQ11 VSSQ
DQ10 DQ9 VDDQ
DQ8 NC VSS
DQMH CLK CKE
VDDQ DQ0 VDD
VSSQ DQ2 DQ1
VDDQ DQ4 DQ3
VSSQ DQ6 DQ5
VDD DQML DQ7
CAS RAS WE
BA0 BA1 CS
G
H
J
NC
A8
A11
A7
A9
A6
A4
A0
A3
A1
A10
VSS
A5
A2 VDD
PIN DESCRIPTIONS
A0-A11
A0-A8
BA0, BA1
DQ0 to DQ15
CLK
Row Address Input
WE
WriteEnable
Column Address Input
Bank Select Address
Data I/O
DQML
DQMH
VDD
x16 Lower Byte Input/Output Mask
x16 Upper Byte Input/Output Mask
Power
System Clock Input
Clock Enable
Vss
Ground
CKE
VDDQ
VssQ
NC
Power Supply for I/O Pin
Ground for I/O Pin
CS
Chip Select
RAS
RowAddressStrobeCommand
ColumnAddressStrobeCommand
NoConnection
CAS
Integrated Silicon Solution, Inc. — www.issi.com
5
Rev. E
07/28/08
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
