IS42S81600D, IS42S16800D
DEVICE OVERVIEW
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE func-
tionenabled. Prechargeonebankwhileaccessingoneofthe
otherthreebankswillhidetheprechargecyclesandprovide
seamless,high-speed,random-accessoperation.
The 128Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 3.3V VDD
and 3.3V VDDQ memory systems containing 134,217,728
bits. Internally configured as a quad-bank DRAM with a
synchronous interface. Each 33,554,432-bit bank is orga-
nizedas4,096rowsby512columnsby16bitsor4,096rows
by 1,024 columns by 8 bits.
SDRAMreadandwriteaccessesareburstorientedstartingat
aselectedlocationandcontinuingforaprogrammednum-
ber of locations in a programmed sequence. The registra-
tionofanACTIVEcommandbeginsaccesses, followedby
a READ or WRITE command. The ACTIVE command in
conjunction with address bits registered are used to select
the bank and row to be accessed (BA0, BA1 select the
bank; A0-A11 select the row). The READ or WRITE
commands in conjunction with address bits registered are
used to select the starting column location for the burst
access.
The128MbSDRAMincludesanAUTOREFRESHMODE,
and a power-saving, power-down mode. All signals are
registeredonthepositiveedgeoftheclocksignal,CLK. All
inputs and outputs are LVTTL compatible.
The 128Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation,theabilitytointerleavebetweeninternalbanks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
ProgrammableREADorWRITEburstlengthsconsistof1,
2, 4 and 8 locations or full page, with a burst terminate
option.
FUNCTIONAL BLOCK DIAGRAM (FOR 2MX16X4 BANKS ONLY)
CLK
CKE
CS
RAS
CAS
WE
DQML
DQMH
DATA IN
BUFFER
COMMAND
DECODER
&
CLOCK
GENERATOR
16
16
2
REFRESH
CONTROLLER
MODE
REGISTER
DQ 0-15
12
V
DD/VDDQ
ss/Vss
SELF
DATA OUT
BUFFER
REFRESH
V
Q
A10
A11
A9
CONTROLLER
16
16
A8
A7
A6
REFRESH
COUNTER
A5
A4
4096
A3
A2
A1
A0
BA0
BA1
4096
MEMORY CELL
ARRAY
4096
4096
12
BANK 0
ROW
ADDRESS
LATCH
ROW
ADDRESS
BUFFER
12
12
SENSE AMP I/O GATE
512
(x 16)
COLUMN
ADDRESS LATCH
BANK CONTROL LOGIC
9
BURST COUNTER
COLUMN DECODER
COLUMN
ADDRESS BUFFER
9
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
