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IC42S16160B-7TL 参数 Datasheet PDF下载

IC42S16160B-7TL图片预览
型号: IC42S16160B-7TL
PDF下载: 下载PDF文件 查看货源
内容描述: 256兆位同步DRAM [256-MBIT SYNCHRONOUS DRAM]
分类和应用: 动态存储器
文件页数/大小: 62 页 / 768 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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IS42S83200B, IS42S16160B  
Initialization  
FUNCTIONAL DESCRIPTION  
SDRAMs must be powered up and initialized in a  
predefinedmanner.  
The256MbSDRAMsarequad-bankDRAMswhichoperate  
at3.3Vandincludeasynchronousinterface(allsignalsare  
registered on the positive edge of the clock signal, CLK).  
Each of the 67,108,864-bit banks is organized as 8,192  
rows by 512 columns by 16 bits or 8,192 rows by 1,024  
columns by 8 bits.  
The 256Mb SDRAM is initialized after the power is applied  
to VDD and VDDQ (simultaneously) and the clock is stable  
with DQM High and CKE High.  
A 200µs delay is required prior to issuing any command  
other than a COMMAND INHIBIT or aNOP. The COMMAND  
INHIBITorNOPmaybeappliedduringthe200usperiodand  
should continue at least through the end of the period.  
Read and write accesses to the SDRAM are burst oriented;  
accesses start at a selected location and continue for a  
programmed number of locations in a programmed  
sequence. Accesses begin with the registration of an AC-  
TIVEcommandwhichisthenfollowedbyaREADorWRITE  
command. The address bits registered coincident with the  
ACTIVE command are used to select the bank and row to  
With at least one COMMAND INHIBIT or NOP command  
havingbeenapplied,aPRECHARGEcommandshouldbe  
appliedoncethe200µsdelayhasbeensatisfied. Allbanks  
mustbeprecharged. Thiswillleaveallbanksinanidlestate  
after which at least eight AUTO REFRESH cycles must be  
performed. After the AUTO REFRESH cycles are complete,  
the SDRAM is then ready for mode register programming.  
beaccessed(BA0andBA1selectthebank,A0-A12selecttherow)  
.
TheaddressbitsA0-A9 (x8);A0-A8(x16)registeredcoincident  
with the READ or WRITE command are used to select the  
starting column location for the burst access.  
The mode register should be loaded prior to applying any  
operational command because it will power up in an un-  
known state.  
Prior to normal operation, the SDRAM must be initialized.  
The following sections provide detailed information covering  
device initialization, register definition, command  
descriptions and device operation.  
20  
Integrated Silicon Solution, Inc. — www.issi.com  
Rev. D  
07/28/08  
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