IS42S83200B, IS42S16160B
REGISTER DEFINITION
Mode Register
Mode register bits M0-M2 specify the burst length, M3
specifiesthetypeofburst(sequentialorinterleaved), M4-M6
specify the CAS latency, M7 and M8 specify the operating
mode,M9specifiestheWRITEburstmode,andM10,M11,
and M12 are reserved for future use.
The mode register is used to define the specific mode of
operation of the SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency, an
operatingmodeandawriteburstmode,asshowninMODE
REGISTERDEFINITION.
The mode register must be loaded when all banks are idle,
and the controller must wait the specified time before
initiatingthesubsequentoperation.Violatingeitherofthese
requirements will result in unspecified operation.
The mode register is programmed via the LOAD MODE
REGISTER command and will retain the stored information
until it is programmed again or the device loses power.
MODE REGISTER DEFINITION
Address Bus (Ax)
BA1 BA0 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode Register (Mx)
Reserved(1)
Burst Length
M2 M1 M0
M3=0
M3=1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full Page Reserved
Burst Type
M3
Type
0
1
Sequential
Interleaved
Latency Mode
M6 M5 M4
CAS Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Operating Mode
M8 M7 M6-M0 Mode
0
—
0
—
Defined Standard Operation
All Other States Reserved
—
Write Burst Mode
M9
0
Mode
Programmed Burst Length
Single Location Access
1. To ensure compatibility with future devices,
should program BA1, BA0, A12, A11, A10 = "0"
1
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Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
07/28/08
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
