IS42S16100E, IC42S16100E
Write Cycle
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CLK
t
CHI
tCKS
t
CK
tCL
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
tAS
tAH
(1)
ROW
ROW
COLUMN
ROW
A0-A9
BANK 0 AND 1
BANK 0 OR 1
t
AS
t
AH
AH
NO PRE
BANK 1
ROW
A10
A11
t
tAS
BANK 1
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
BANK 0
t
CS
t
CH
DQM
DQ
t
DH
tDS
tDS
t
DH
t
DS
t
DH
tDS
tDH
D
IN
m
D
IN m+2
D
IN m+3
D
IN m+1
t
RCD
RAS
RC
t
DPL
t
RCD
RAS
RC
t
RP
t
t
t
t
<
PRE
>
<ACT>
<
WRIT>
<ACT>
PALL
Undefined
Don't Care
CAS latency = 3, burst length = 4
Note 1: A8,A9 = Don’t Care.
64
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08