IS42S16100E, IC42S16100E
Write Cycle / Ping-Pong Operation
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
t
CKS
tCK
tCL
CKE
CS
t
t
CKA
CH
tCS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
AS
AS
tAH
(1)
(1)
ROW
ROW
COLUMN
ROW
ROW
ROW
COLUMN
A0-A9
t
AUTO PRE
AUTO PRE
t
AH
AH
ROW
A10
A11
NO PRE
BANK 1
BANK 0 OR 1
BANK 0
NO PRE
BANK 0
t
t
AS
BANK 0
BANK 0
BANK 1
tCH
tCS
DQM
DQ
tDS
t
DS
tDS
tDS
tDS
t
DS
t
DS
tDS
DH
t
DH
t
DH
t
DH
t
DH
t
DH
t
DH
t
t
DH
D
IN 0m
D
IN 0m+1
D
IN 0m+2
D
IN 0m+3
D
IN 1m
D
IN 1m+1
D
IN 1m+2
D
IN 1m+3
t
RRD
(BANK 0 TO 1)
RCD
(BANK 0)
tDPL
t
DPL
t
t
RCD
t
RCD
(BANK 1)
(BANK 0)
t
RP
t
RAS
t
RAS
(BANK 0)
(BANK 0)
(BANK 0)
t
RC
t
RC
(BANK 0)
(BANK 0)
t
RAS
(BANK 1)
t
RC
(BANK 1)
<
ACT 0>
<ACT 1>
<
WRIT 0
WRITA 0
>
<
WRIT 1
>
<PRE 0
>
<ACT 0>
Undefined
Don't Care
CAS latency = 2, burst length = 2
Note 1: A8,A9 = Don’t Care.
48
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08