欢迎访问ic37.com |
会员登录 免费注册
发布采购

IC42S16100E-6TL 参数 Datasheet PDF下载

IC42S16100E-6TL图片预览
型号: IC42S16100E-6TL
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 1MX16, 5.5ns, CMOS, PDSO50, 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-50]
分类和应用: 时钟动态存储器光电二极管内存集成电路
文件页数/大小: 81 页 / 1082 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
 浏览型号IC42S16100E-6TL的Datasheet PDF文件第14页浏览型号IC42S16100E-6TL的Datasheet PDF文件第15页浏览型号IC42S16100E-6TL的Datasheet PDF文件第16页浏览型号IC42S16100E-6TL的Datasheet PDF文件第17页浏览型号IC42S16100E-6TL的Datasheet PDF文件第19页浏览型号IC42S16100E-6TL的Datasheet PDF文件第20页浏览型号IC42S16100E-6TL的Datasheet PDF文件第21页浏览型号IC42S16100E-6TL的Datasheet PDF文件第22页  
IS42S16100E, IC42S16100E  
(1)  
CKE RELATED COMMAND TRUTH TABLE  
CKE  
n-1  
Current State  
Operation  
n
X
H
H
H
H
L
CS RAS CAS WE A11 A10 A9-A0  
Self-Refresh  
Undefined  
H
L
X
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Self-Refresh Recovery(2)  
Self-Refresh Recovery(2)  
Illegal(2)  
L
L
L
Illegal(2)  
L
L
X
X
X
H
L
Self-Refresh  
L
X
H
L
X
X
H
H
L
Self-Refresh Recovery  
Idle State After tr c Has Elapsed  
Idle State After tr c Has Elapsed  
Illegal  
H
H
H
H
H
H
H
H
L
H
H
H
H
L
L
Illegal  
L
X
X
H
L
Power-Down on the Next Cycle  
Power-Down on the Next Cycle  
Illegal  
H
L
X
H
H
L
L
L
L
Illegal  
L
L
X
X
X
X
X
Clock Suspend Termination on the Next Cycle (2)  
H
L
X
X
X
X
X
X
X
X
Clock Suspend  
Undefined  
L
Power-Down  
H
L
X
H
Power-Down Mode Termination, Idle After  
That Termination(2)  
Power-Down Mode  
L
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
L
X
H
L
X
X
H
L
X
X
X
H
L
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
Both Banks Idle  
No Operation  
X
See the Operation Command Table  
Bank Active Or Precharge  
Auto-Refresh  
X
L
X
L
L
X
Mode Register Set  
L
L
L
OP CODE  
See the Operation Command Table  
See the Operation Command Table  
See the Operation Command Table  
Self-Refresh(3)  
H
L
X
H
L
X
X
H
L
X
X
X
H
L
X
X
X
X
X
X
X
X
X
L
X
L
L
X
L
L
L
X
See the Operation Command Table  
Power-Down Mode(3)  
L
L
L
L
OP CODE  
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Other States  
See the Operation Command Table  
Clock Suspend on the Next Cycle(4)  
Clock Suspend Termination on the Next Cycle  
H
H
L
H
L
Clock Suspend Termination on the Next CycleL  
Notes:  
1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input  
2. The CLK pin and the other input are reactivated asynchronously by the transition of the CKE level from LOW to HIGH.  
The minimum setup time (tc k a ) required before all commands other than mode termination must be satisfied.  
3. Both banks must be set to the inactive (idle) state in advance to switch to power-down mode or self-refresh mode.  
4. The input must be command defined in the operation command table.  
18  
Integrated Silicon Solution, Inc. — www.issi.com  
Rev. C  
01/22/08  
 复制成功!