IC41SV4105
Functional Description
Refresh Cycle
The IC41SV4105 are CMOS DRAMs optimized for high-
speed bandwidth, low power applications. During READ
or WRITE cycles, each bit is uniquely addressed through
the 10 address bits. These are entered 10 bits (A0-A9) at
a time. The row address is latched by the Row Address
Strobe (RAS). The column address is latched by the
Column Address Strobe (CAS). RAS is used to latch the
first ten bits and CAS is used the latter ten bits.
To retain data, 1,024 refresh cycles are required in each
16 ms period . There are two ways to refresh the memory:
1. By clocking each of the 1,024 row addresses (A0
through A9) with RAS at least once every 16 ms . Any
read, write, read-modify-write or RAS-only cycle re-
freshes the addressed row.
2. Using a CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 10-bit counter provides the row ad-
dresses and the external address inputs are ignored.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or aborted
before the minimum tRAS time has expired. A new cycle
must not be initiated until the minimum precharge time tRP,
tCP has elapsed.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Power-On
Read Cycle
After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS signal).
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time specified
by tAR. Data Out becomes valid only when tRAC, tAA, tCAC
and tOE are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
During power-on, it is recommended that RAS track with
VCC or be held at a valid VIH to avoid current surges.
Write Cycle
A write cycle is initiated by the falling edge of CAS and WE,
whichever occurs last. The input data must be valid at or
before the falling edge of CAS or WE, whichever occurs
last.
4
Integrated Circuit Solution Inc.
DR032-0A 10/29/2001
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
