IC41SV4105
Preliminary
1M x 4 (4−MBIT) DYNAMIC RAM
WITH FAST PAGE MODE
FEATURES
DESCRIPTION
• Fast Page Mode Access Cycle
• TTL compatible inputs and outputs
• Refresh Interval:
The ICSI 4105 Series is a 1,048,576 x 4-bit high-performance
CMOS Dynamic Random Access Memory. The Fast Page
Mode allows 1,024 random accesses within a single row with
access cycle time as short as 20 ns per 4-bit word.
-- 1,024 cycles/16 ms
• Refresh Mode: RAS-Only,
CAS-before-RAS (CBR), and Hidden
• JEDEC standard pinout
• Single power supply:
These features make the 4105 Series ideally suited for digital
signal processing, and low power portable audio applications.
The 4105 Series is packaged in a 20-pin 300mil SOJ and a 20
pin TSOP-2
1.9V − 2.4V
KEY TIMING PARAMETERS
Parameter
RAS Access Time (tRAC)
-50 -70 -100 Unit
50
70 100 ns
CAS Access Time (tCAC)
Column Address Access Time (tAA) 25
14
20
35
45
25
50
60
ns
ns
ns
Fast Page Mode Cycle Time (tPC)
Read/Write Cycle Time (tRC)
20
90 130 180 ns
PIN CONFIGURATION
20 (26) Pin SOJ, TSOP-2
PIN DESCRIPTIONS
A0-A9
I/O0-3
WE
Address Inputs
I/O0
I/O1
WE
RAS
A9
1
2
3
4
5
26
25
24
23
22
GND
I/O3
I/O2
CAS
OE
Data Inputs/Outputs
Write Enable
OE
Output Enable
RAS
CAS
Vcc
Row Address Strobe
Column Address Strobe
Power
A0
A1
9
18
17
16
15
14
A8
A7
A6
A5
A4
GND
Ground
10
11
12
13
A2
A3
VCC
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
DR032-0A 10/29/2001
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
