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IC41C82002S-50T 参数 Datasheet PDF下载

IC41C82002S-50T图片预览
型号: IC41C82002S-50T
PDF下载: 下载PDF文件 查看货源
内容描述: [EDO DRAM, 2MX8, 50ns, CMOS, PDSO28, 0.400 INCH, TSOP2-28]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 19 页 / 494 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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IC41C82002S  
IC41LV82002S  
ELECTRICAL CHARACTERISTICS(1)  
(Recommended Operating Conditions unless otherwise noted.)  
Symbol Parameter  
Test Condition  
Speed Min. Max.  
Unit  
IIL  
Input Leakage Current  
Any input 0V VIN Vcc  
Other inputs not under test = 0V  
–5  
–5  
2.4  
5
µA  
IIO  
Output Leakage Current  
Output High Voltage Level  
Output Low Voltage Level  
Standby Current: TTL  
Output is disabled (Hi-Z)  
0V VOUT Vcc  
5
µA  
V
VOH  
VOL  
ICC1  
ICC2  
ICC3  
IOH = –5.0 mA with VCC=5V  
IOH = –2.0 mA with VCC=3.3V  
0.4  
IOL = 4.2 mA with VCC=5V  
IOL = 2 mA with VCC=3.3V  
V
RAS, CAS VIH  
5V  
3.3V  
2
0.5  
mA  
mA  
mA  
Standby Current: CMOS  
RAS, CAS VCC – 0.2V  
5V  
3.3V  
1
0.5  
Operating Current:  
RAS, CAS,  
Address Cycling, tRC = tRC (min.)  
-50  
-60  
120  
110  
Random Read/Write(2,3,4)  
Average Power Supply Current  
ICC4  
ICC5  
ICC6  
Operating Current:  
RAS = VIL, CAS Cycling,  
tRC = tRC (min.)  
-50  
-60  
90  
80  
mA  
mA  
mA  
EDO Page Mode(2,3,4)  
Average Power Supply Current  
Refresh Current:  
RAS Cycling, CAS VIH  
tRC = tRC (min.)  
-50  
-60  
120  
110  
RAS-Only(2,3)  
Average Power Supply Current  
Refresh Current:  
RAS, CAS Cycling  
tRC = tRC (min.)  
-50  
-60  
120  
110  
CBR(2,3,5)  
Average Power Supply Current  
ICCS  
Self Refresh Current  
Self Refresh Mode  
5V  
300  
300  
µA  
µA  
3.3V  
Notes:  
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device  
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.  
2. Dependent on cycle rates.  
3. Specified values are obtained with minimum cycle time and the output open.  
4. Column-address is changed once each EDO page cycle.  
5. Enables on-chip refresh and address counters.  
6
Integrated Circuit Solution Inc.  
DR022-0A 08/20/2001