IC41C82002S
IC41LV82002S
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50
-60
Symbol
Parameter
Min. Max.
Min. Max.
Units
tACH
Column-Address Setup Time to CAS
Precharge during WRITE Cycle
15
—
15
—
ns
tOEH
OE Hold Time from WE during
READ-MODIFY-WRITE cycle(18)
8
—
10
—
ns
tDS
Data-In Setup Time(15, 22)
Data-In Hold Time(15, 22)
0
8
—
—
—
—
0
—
—
—
—
ns
ns
ns
ns
tDH
10
tRWC
tRWD
READ-MODIFY-WRITE Cycle Time
108
64
133
77
RAS to WE Delay Time during
READ-MODIFY-WRITE Cycle(14)
tCWD
tAWD
tPC
CAS to WE Delay Time(14, 20)
Column-Address to WE Delay Time(14)
26
39
20
—
—
—
32
47
25
—
—
—
ns
ns
ns
EDO Page Mode READ or WRITE
Cycle Time
tRASP
tCPA
RAS Pulse Width in EDO Page Mode
Access Time from CAS Precharge(15)
50
—
56
100K
30
60
—
68
100K
35
ns
ns
ns
tPRWC
EDO Page Mode READ-WRITE
Cycle Time
—
—
tCOH
tOFF
Data Output Hold after CAS LOW
5
0
—
5
0
—
ns
ns
Output Buffer Turn-Off Delay from
CAS or RAS(13,15,19, 24)
12
15
tWHZ
tCSR
tCHR
tORD
Output Disable Delay from WE
3
5
8
0
10
—
—
—
3
5
10
—
—
—
ns
ns
ns
ns
CAS Setup Time (CBR REFRESH)(20, 25)
CAS Hold Time (CBR REFRESH)( 21, 25)
10
0
OE Setup Time prior to RAS during
HIDDEN REFRESH Cycle
tREF
Auto Refresh Period
2,048 Cycles
—
1
32
50
—
1
32
50
ms
ns
tT
Transition Time (Rise or Fall)(2, 3)
AC TEST CONDITIONS
Output load:
Two TTL Loads and 50 pF (Vcc = 5.0V + 10%)
One TTL Load and 50 pF (Vcc = 3.3V + 10%)
Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V + 10%)
VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V + 10%)
Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5.0V + 10%, 3.3V + 10%)
8
Integrated Circuit Solution Inc.
DR022-0A 08/20/2001
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
