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IC24C64A-2ZI 参数 Datasheet PDF下载

IC24C64A-2ZI图片预览
型号: IC24C64A-2ZI
PDF下载: 下载PDF文件 查看货源
内容描述: [EEPROM, 8KX8, Serial, CMOS, PDSO8, TSSOP-8]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
文件页数/大小: 12 页 / 54 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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IS24C32A  
®
IS24C64A/B  
ISSI  
READ OPERATION  
Random Address Read  
Read operations are initiated in the same manner as Write  
operations, except that the (R/W) bit of the Slave address  
issetto1”. TherearethreeReadoperationoptions:current  
addressread, randomaddressreadandsequentialread.  
Selective Read operations allow the Master device to  
select at random any memory location for a Read  
operation. The Master device first performs a 'dummy'  
Write operation by sending the Start condition, Slave  
address and byte address of the location it wishes to read.  
After the IS24C32A/64A/64B acknowledges the byte  
address,theMasterdeviceresendstheStartconditionand  
the Slave address, this time with the R/W bit set to  
one. TheEEPROMthenrespondswithitsACKandsends  
the data requested. The Master device does not send an  
ACKbutwillgenerateaStopcondition. (RefertoFigure9.  
RandomAddressReadDiagram.)  
Current Address Read  
TheIS24C32A/64A/64Bcontainsaninternaladdresscounter  
which maintains the address of the last byte accessed,  
incrementedbyone. Forexample,ifthepreviousoperation  
iseitheraReadorWriteoperationaddressedtotheaddress  
locationn, theinternaladdresscounterwouldincrementto  
address location n+1. When the EEPROM receives the  
Slave Addressing Byte with a Read operation (R/W bit set  
to1”),itwillrespondanACKandtransmitthe8-bitdatabyte  
stored at address location n+1. The Master should not  
acknowledge the transfer but should generate a Stop  
condition so the IS24C32A/64A/64B discontinues  
transmission. If 'n' is the last byte of the memory, then the  
datafromlocation'0'willbetransmitted. (RefertoFigure8.  
CurrentAddressReadDiagram.)  
Sequential Read  
Sequential Reads can be initiated as either a Current  
Address Read or Random Address Read. After the  
IS24C32A/64A/64Bsendsinitialbytesequence,theMaster  
device now responds with an ACK indicating it requires  
additionaldatafromtheIS24C32A/64A/64B.TheEEPROM  
continues to output data for each ACK received. The  
MasterdeviceterminatesthesequentialReadoperationby  
pulling SDA High (no ACK) indicating the last data word to  
be read, followed by a Stop condition.  
Thedataoutputissequential, withthedatafromaddressn  
followed by the data from address n+1, n+2 ... etc. The  
addresscounterincrementsbyoneautomatically,allowing  
the entire memory contents to be serially read during  
sequential Read operation. When the memory address  
boundary of 8191 for IS24C64A/B or 4095 for IS24C32A  
(dependingonthedevice)isreached,theaddresscounter  
“rollsovertoaddress0,andthedevicecontinuestooutput  
data. (Refer to Figure 10. Sequential Read Diagram).  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
ADVANCEDINFORMATION Rev. 00A  
5
01/26/04