IS24C32A
®
IS24C64A/B
ISSI
FUNCTIONAL BLOCK DIAGRAM
HIGH VOLTAGE
8
Vcc
GENERATOR,
TIMING & CONTROL
5
6
7
SDA
SCL
WP
CONTROL
LOGIC
EEPROM
ARRAY
SLAVE ADDRESS
REGISTER &
COMPARATOR
1
2
3
WORD ADDRESS
COUNTER
A0
A1
A2
Y
DECODER
ACK
Clock
DI/O
DATA
REGISTER
4
GND
>
nMOS
PIN DESCRIPTIONS
PIN CONFIGURATION
8-Pin DIP, SOIC, and TSSOP
A0-A2
SDA
SCL
WP
Address Inputs
Serial Address/Data I/O
A0
A1
1
2
3
4
8
7
6
5
VCC
WP
Serial Clock Input
Write Protect Input
Power Supply
Ground
Vcc
A2
SCL
SDA
GND
GND
SCL
This input clock pin is used to synchronize the data
transfer to and from the device.
withthe24C16.Whenpinsarehardwired,asmanyaseight
32K/64K devices may be addressed on a single bus
system.Whenthepinsarenothardwired,thedefaultvalues
of A0, A1, and A2 are zero.
SDA
The SDA is a Bi-directional pin used to transfer addresses
anddataintoandoutofthedevice. TheSDApinisanopen
drain output and can be wire-Ored with other open drain
or open collector outputs. The SDA bus requires a pullup
resistor to Vcc.
WP
WPistheWriteProtectpin. WithIS24C32A/64A, iftheWP
pinistiedtoVcc, theentirearraybecomesWriteProtected
(Read only). With IS24C64B, if WP is tied to Vcc, the top
quarterofthearray(1800h-1FFFh)becomesWriteProtected.
When WP is tied to GND or left floating, normal read/write
operations are allowed to the device.
A0, A1, A2
The A0, A1 and A2 are the device address inputs that are
hardwired or left not connected for hardware compatibility
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCEDINFORMATION Rev. 00A
01/26/04
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
