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IC24C64A-2ZI 参数 Datasheet PDF下载

IC24C64A-2ZI图片预览
型号: IC24C64A-2ZI
PDF下载: 下载PDF文件 查看货源
内容描述: [EEPROM, 8KX8, Serial, CMOS, PDSO8, TSSOP-8]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
文件页数/大小: 12 页 / 54 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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IS24C32A  
®
IS24C64A/B  
ISSI  
DEVICE OPERATION  
Stop Condition  
IS24C32A/64A/64B features serial communication and  
supports a bi-directional 2-wire bus transmission protocol.  
The Stop condition is defined as a Low to High transition of  
SDAwhenSCLisHigh. AlloperationsmustendwithaStop  
condition.  
2-WIRE BUS  
Acknowledge (ACK)  
Thetwo-wirebusisdefinedasaSerialDataline(SDA),and  
a Serial Clock line (SCL). The protocol defines any device  
that sends data onto the SDA bus as a transmitter, and the  
receiving devices as a receiver. The bus is controlled by a  
Master device that generates the SCL, controls the bus  
access, andgeneratestheStopandStartconditions. The  
IS24C32A/64A/64B is the Slave device on the bus.  
After a successful data transfer, each receiving device is  
required to generate an ACK. The Acknowledging device  
pulls down the SDA line.  
Reset  
The IS24C32A/64A/64B contains a reset function in case  
the 2-wire bus transmission is accidentally interrupted  
(eg. a power loss), or needs to be terminated mid-stream.  
The reset is caused when the Master device creates a  
Start condition. To do this, it may be necessary for the  
Master device to monitor the SDA line, which may cycle  
the SCL up to nine times. (For each clock signal  
transition to High, the Master checks for a High level on  
SDA.)  
The Bus Protocol:  
– Data transfer may be initiated only when the bus is not  
busy  
– During a data transfer, the data line must remain stable  
whenevertheclocklineishigh. Anychangesinthedata  
line while the clock line is high will be interpreted as a  
Start or Stop condition.  
Standby Mode  
The state of the data line represents valid data after a Start  
condition.Thedatalinemustbestableforthedurationofthe  
High period of the clock signal. The data on the SDA line  
may be changed during the Low period of the clock signal.  
Thereisoneclockpulseperbitofdata. Eachdatatransfer  
isinitiatedwithaStartconditionandterminatedwithaStop  
condition.  
Power consumption is reduced in standby mode. The  
IS24C32A/64A/64Bwillenterstandbymode: a)AtPower-  
up, and remain in it until SCL or SDA toggles; b) Following  
the Stop signal if a no write operation is initiated; or c)  
Followinganyinternalwriteoperation.  
Start Condition  
The Start condition precedes all commands to the device  
andisdefinedasaHightoLowtransitionofSDAwhenSCL  
isHigh.TheEEPROMmonitorstheSDAandSCLlinesand  
will not respond until the Start condition is met.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
ADVANCEDINFORMATION Rev. 00A  
3
01/26/04