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AS7C33512PFS16A-150TQI 参数 Datasheet PDF下载

AS7C33512PFS16A-150TQI图片预览
型号: AS7C33512PFS16A-150TQI
PDF下载: 下载PDF文件 查看货源
内容描述: [Standard SRAM, 512KX16, 10ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100]
分类和应用: 静态存储器内存集成电路
文件页数/大小: 13 页 / 268 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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AS7C33512PFS16A  
AS7C33512PFS18A  
®
.
Timing characteristics for 2.5 V I/ O operation  
–166  
–150  
–133  
–100  
Parameter  
Symbol Min Max Min Max Min Max Min Max Unit Notes1  
Clock frequency  
fMax  
tCYC  
tCYCF  
tCD  
6
166  
6.6  
10  
-
150  
7.5  
12  
-
133  
10  
12  
-
100 MHz  
Cycle time (pipelined mode)  
ns  
ns  
Cycle time (flow-through mode)  
Clock access time (pipelined mode)  
Clock access time (flow-through mode)  
Output enable low to data valid  
10  
-
3.8  
9
4.0  
10  
3.8  
4.2  
10  
4.0  
5.0 ns  
12 ns  
5.0 ns  
tCDF  
tOE  
tLZC  
tOH  
3.5  
Clock high to output low Z  
0
0
0
0
ns  
ns  
2,3,4  
2
Data output invalid from clock high (Pipelined Mode)  
1.5  
1.5  
1.5  
1.5  
tOHF  
Data Output invalid from clock high (Flow-through  
Mode)  
3.0  
3.0  
3.0  
3.0  
ns  
ns  
2
Output enable low to output low Z  
Output enable high to output high Z  
Clock high to output high Z  
Output enable high to invalid output  
Clock high pulse width  
tLZOE  
tHZOE  
tHZC  
tOHOE  
tCH  
0
3.5  
3.5  
0
3.8  
3.8  
0
4.0  
4.0  
0
2,3,4  
2,3,4  
2,3,4  
4.5 ns  
5.0 ns  
0
0
0
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
2.4  
2.3  
1.7  
1.7  
1.7  
1.7  
0.7  
0.7  
0.7  
0.7  
1.7  
1.7  
2.5  
2.5  
1.7  
1.7  
1.7  
1.7  
0.7  
0.7  
0.7  
0.7  
1.7  
1.7  
1.7  
0.7  
0.7  
0.7  
2.5  
2.5  
1.7  
1.7  
1.7  
1.7  
0.7  
0.7  
0.7  
0.7  
1.7  
1.7  
1.7  
0.7  
0.7  
0.7  
3.5  
3.5  
2.0  
2.0  
2.0  
2.0  
0.7  
0.7  
0.7  
0.7  
2.0  
2.0  
2.0  
0.7  
0.7  
0.7  
5
5
Clock low pulse width  
tCL  
Address setup to clock high  
Data setup to clock high  
tAS  
6
tDS  
6
Write setup to clock high  
Chip select setup to clock high  
Address hold from clock high  
Data hold from clock high  
Write hold from clock high  
Chip select hold from clock high  
ADV setup to clock high  
tWS  
6,7  
6,8  
6
tCSS  
tAH  
tDH  
6
tWH  
tCSH  
tADVS  
tADSPS  
6,7  
6,8  
6
ADSP setup to clock high  
6
ADSC setup to clock high  
tADSCS 1.7  
6
ADV hold from clock high  
ADSP hold from clock high  
ADSC hold from clock high  
1 See “Notes on page 11.  
tADVH  
0.7  
0.7  
6
tADSPH  
6
tADSCH 0.7  
6
5/ 9/ 03, v.1.8.1  
Alliance Semiconductor  
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