AS7C33512PFS16A
AS7C33512PFS18A
®
Signal descriptions
Signal
I/ O
Properties
CLOCK
SYNC
Description
CLK
I
I
Clock. All inputs except OE, FT, ZZ, LBO are synchronous to this clock.
Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.
Data. Driven as output when the chip is enabled and OE is active.
A0–A18
DQ[a,b]
I/ O
SYNC
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When
CE0 is inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more
information.
CE0
I
SYNC
Synchronous chip enables. Active high and active low, respectively. Sampled on clock
edges when ADSC is active or when CE0 and ADSP are active.
CE1, CE2
ADSP
I
I
SYNC
SYNC
Address strobe (processor). Asserted low to load a new address or to enter standby
mode.
Address strobe (controller). Asserted low to load a new address or to enter standby
mode.
ADSC
ADV
I
I
I
SYNC
SYNC
SYNC
Burst advance. Asserted low to continue burst read/ write.
Global write enable. Asserted low to write all 16 or 18 bits. When high, BWE and
BW[a,b] control write enable.
GWE
Byte write enable. Asserted low with GWE = high to enable effect of BW[a,b]
inputs.
BWE
BW[a,b]
OE
I
I
I
I
SYNC
SYNC
Write enables. Used to control write of individual bytes when GWE = high and
BWE = low. If any of BW[a,b] is active with GWE = high and BWE = low the cycle
is a write cycle. If all BW[a,b] are inactive, the cycle is a read cycle.
Asynchronous output enable. I/ O pins are driven when OE is active and the chip is
in read mode.
ASYNC
STATIC
Count mode. When driven high, count sequence follows Intel XOR convention.
When driven low, count sequence follows linear convention. This signal is internally
pulled high.
LBO
Flow-through mode.When low, enables single register flow-through mode. Connect
to VDD if unused or for pipelined operation.
FT
I
I
STATIC
ASYNC
Snooze. Places device in low power mode; data is retained. Connect to GND if
unused.
ZZ
Absolute maximum ratings
Parameter
Symbol
Min
–0.5
–0.5
–0.5
–
Max
+4.6
Unit
V
Power supply voltage relative to GND
Input voltage relative to GND (input pins)
Input voltage relative to GND (I/ O pins)
Power dissipation
VDD, VDDQ
V
VDD + 0.5
VDDQ + 0.5
1.8
V
IN
V
V
IN
PD
W
DC output current
IOUT
Tstg
–
50
mA
° C
° C
Storage temperature (plastic)
Temperature under bias
–65
–65
+150
Tbias
+135
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional oper-
ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions may affect reliability.
5/ 9/ 03, v.1.8.1
Alliance Semiconductor
3 of 13
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
