AS7C33512NTD16A
AS7C33512NTD18A
®
Timing characteristics for 3.3 V I/O operation
–166
Parameter
Clock frequency
Cycle time (pipelined mode)
Cycle time (flow-through mode)
Clock access time (pipelined mode)
Clock access time (flow-through mode)
Output enable low to data valid
Clock high to output low Z
Data output invalid from clock high
Output enable low to output low Z
Output enable high to output high Z
Clock high to output high Z
Output enable high to invalid output
Clock high pulse width
Clock low pulse width
Address setup to clock high
Data setup to clock high
Write setup to clock high
Chip select setup to clock high
ADV/LD
setup to clock high
–150
Min
Max
–133
Min
Max
–100
Min
Max
Symbol
f
Max
t
CYC
t
CYCF
t
CD
t
CDF
t
OE
t
LZC
t
OH
t
LZOE
t
HZOE
t
HZC
t
OHOE
t
CH
t
CL
t
AS
t
DS
t
WS
t
CSS
t
ADVS
t
CENS
t
AH
t
DH
t
WH
t
CSH
t
ADVH
t
CENH
Min
Max
Unit Notes
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
5
6
6
6,7
6,8
6
6
6
6
6,7
6,8
6
6
2,3,4
2
2,3,4
2,3,4
2,3,4
–
6
10
–
–
–
0
1.5
0
–
–
0
2.4
2.2
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
166
–
–
3.5
9
3.5
–
–
–
3.5
3.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
6.6
10
–
–
–
0
1.5
0
–
–
0
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
150
–
–
3.8
10
3.8
–
–
–
3.8
3.8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
7.5
12
–
–
–
0
1.5
0
–
–
0
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
133
–
–
4.0
10
4.0
–
–
–
4.0
4.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
10
12
–
–
–
0
1.5
0
–
–
0
3.5
3.5
2.0
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
100 MHz
–
–
5.0
12
5.0
–
–
–
4.5
5.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Clock enable setup to clock high
Address hold from clock high
Data hold from clock high
Write hold from clock high
Chip select hold from clock high
ADV/LD
hold from clock high
Clock enable hold from clock high
1 Refer to “notes” on page 11.
4/1/03, v.1.9.4
Alliance Semiconductor
7 of 12
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
