AS7C33512NTD16A
AS7C33512NTD18A
®
Functional description
The AS7C33512NTD16A and 7C33512NTD18A are high performance CMOS 8 Mbit synchronous Static Random Access Memory (SRAM)
devices organized as 524,288 words × 16 or 18 bits and incorporate a LATE LATE Write.
This variation of the 8Mb sychronous SRAM uses the No Turnaround Delay (NTD
™
) architecture, featuring an enhanced write operation that
improves bandwidth over pipelined burst devices. In a normal pipelined burst device, the write data, command, and address are all applied to
the device on the same clock edge. If a read command follows this write command, the system must wait for two 'dead' cycles for valid data to
become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or read-modify-write
operations.
NTD
™
devices use the memory bus more efficiently by introducing a write latency which matches the two-cycle pipelined or one-cycle flow-
through read latency. Write data is applied two cycles after the write command and address, allowing the read pipeline to clear. With NTD
™
,
write and read operations can be used in any order without producing dead bus cycles.
Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 16- or 18-bit
writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device, two
clock cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations. It can be tied low for
normal operations. Outputs go to a high impedance state when the device is deselected by any of the three chip enable inputs (refer to
synchronous truth table on page 4.) In pipelined mode, a two cycle deselect latency allows pending read or write operations to be completed.
Use the ADV/LD (burst advance) input to perform burst read, write and deselect operations. When ADV/LD is high, external addresses, chip
select, R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device
operations, including burst, can be stalled using the CEN=1, the clock enable input.
The AS7C33512NTD16A and 7C33512NTD18A operate with a 3.3V ± 5% power supply for the device core (V
DD
). DQ circuits use a separate
power supply (V
DDQ
) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin 14×20 mm TQFP.
Capacitance
Parameter
Input capacitance
I/O capacitance
Symbol
C
IN
C
I/O
Signals
Address and control pins
I/O pins
Test conditions
V
IN
= 0V
V
IN
= V
OUT
= 0V
Max
5
7
Unit
pF
pF
Burst order
Interleaved Burst Order
LBO=1
A1 A0 A1 A0
Starting Address
First increment
Second increment
Third increment
00
01
10
11
01
00
11
10
A1 A0 A1 A0
10
11
00
01
11
10
01
00
Starting Address
First increment
Second increment
Third increment
Linear Burst Order
LBO=0
A1 A0 A1 A0
00
01
10
11
01
10
11
00
A1 A0 A1 A0
10
11
00
01
11
00
01
10
4/1/03, v.1.9.4
Alliance Semiconductor
3 of 12
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
