AS7C33512NTD16A
AS7C33512NTD18A
®
AC test conditions
• Output load: see Figure B, except for t , t
, t
, t , see Figure C.
LZC LZOE HZOE HZC
• Input pulse level: GND to 3V. See Figure A.
Thevenin equivalent:
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
+3.3V for 3.3V I/ O;
/ +2.5V for 2.5V I/ O
319Ω/1667Ω
Z = 50
Ω
50
Ω
0
D
OUT
V = 1.5V
+3.0V
L
D
OUT
90%
10%
90%
10%
5 pF*
for 3.3V I/ O;
353Ω/1538Ω
30 pF*
= V / 2
DDQ
GND
*including scope
and jig capacitance
GND
for 2.5V I/ O
Figure A: Input waveform
Figure B: Output load (A)
Figure C: Output load(B)
Notes:
1) For test conditions, see “AC Test Conditions”, Figures A, B, C
2) This paracmeter measured with output load conditon in Figure C.
3) This parameter is sampled, but not 100% tested.
4) t
is less than t
and t
is less than t at any given temperature and voltage.
HZOE
LZOE HZC
LZC
5) t measured high above V and t measured as low below V
CH IH CL IL
6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet
the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.
7) Write refers to R/ W, BW[a:b].
8) Chip select refers to CE0, CE1, CE2.
Package dimensions :100-pin quad flat pack (TQFP)
Hd
TQFP
D
Min
0.05
Max
0.15
A1
A2
b
b
e
1.35
1.45
0.22
0.38
α
0.09
0.20
c
13.80
19.80
14.20
20.20
D
E
He
E
0.65 nominal
e
15.80
21.80
0.45
16.20
22.20
0.75
Hd
He
L
A2
c
L1
L
A1
1.00 nominal
L1
0°
7°
α
Dimensions in millimeters
4/ 1/ 03, v.1.9.4
Alliance Semiconductor
11 of 12
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
