February 2003
®
AS7C33512NTD16A
AS7C33512NTD18A
3.3V 512K
×
16/18
65$0 ZLWK 17'
TM
Features
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NTD
™
1
Organization: 524,288 words × 16 or 18 bits
architecture for efficient bus operation
Fast clock speeds to 166 MHz in LVTTL/LVCMOS
Fast clock to data access: 3.5/3.8/4.0/5.0 ns
Fast OE access time: 3.5/3.8/4.0/5.0 ns
Fully synchronous register-to-register operation
Flow-through or pipelined mode
Asynchronous output enable control
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Available in100-pin TQFP
Byte write enables
Multiple chip enables for easy expansion
3.3V core power supply
2.5V or 3.3V I/O operation with separate V
DDQ
30 mW typical standby power in power down mode
Self-timed WRITE cycles
“Interleaved” or “linear burst” modes
Snooze mode for standby operation
1. NTD
™
is a trademark of Alliance Semiconductor Corporation.
Logic block diagram
A[18:0]
19
D
Address
register
Burst logic
CLK
Q
19
D
CE0
CE1
CE2
R/W
BWa
BWb
ADV / LD
FT
LBO
ZZ
Q
Write delay
addr. registers
CLK
CLK
19
Control
logic
Write Buffer
CLK
512K x 16/18
SRAM
Array
DQ [a:b]
16/18
D
Data
Q
Input
Register
CLK
16/18
16/18
16/18
16/18
CLK
CEN
CLK
Output
OE
Register
16/18
OE
DQ[a:b]
Selection guide
-166
Minimum cycle time
Maximum pipelined clock frequency
Maximum pipelined clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
6
166
3.5
475
130
30
–150
6.6
150
3.8
425
110
30
–133
7.5
133
4
400
100
30
–100
10
100
5
300
90
30
Units
ns
MHz
ns
mA
mA
mA
4/1/03
,
v.1.9.4
Alliance Semiconductor
1 of 12
Copyright © Alliance Semiconductor. All rights reserved.
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
