AS7C332MNTD18A
®
Timing characteristics over operating range
-200
-167
-133
1
Parameter
Sym
Unit Notes
Min
Max
200
–
Min
Max
167
–
Min
Max
Clock frequency
F
t
–
–
–
133 MHz
MAX
CYC
Cycle time (pipelined mode)
Cycle time (flow-through mode)
Clock access time (pipelined mode)
Clock access time (flow-through mode)
Output enable low to data valid
Clock high to output low Z
5
6
7.5
12
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
7.5
–
–
8.5
–
–
CYCF
t
3.1
6.5
3.1
–
3.4
7.5
3.4
–
3.8
10
3.8
–
CD
t
–
–
–
CDF
t
–
–
–
OE
t
0
0
0
2,3,4
2
LZC
Data output invalid from clock high (pipelined mode)
t
1.5
3.0
0
–
1.5
3.0
0
–
1.5
3.0
0
–
OH
Data Output invalid from clock high (flow-through mode) t
–
–
–
2
OHF
Output enable low to output low Z
Output enable high to output high Z
Clock high to output high Z
Output enable high to invalid output
Clock high pulse width
t
–
–
–
2,3,4
2,3,4
2,3,4
LZOE
HZOE
t
–
3.0
3.0
–
–
3.4
3.4
–
–
3.8
3.8
–
t
–
–
–
HZC
t
0
0
0
OHOE
t
2.0
2.0
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
1.4
0.4
1.4
0.4
–
2.4
2.3
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
0.5
1.5
0.5
–
2.4
2.4
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
0.5
1.5
0.5
–
5
5
CH
Clock low pulse width
t
t
t
–
–
–
CL
AS
DS
Address and Control setup to clock high
Data setup to clock high
–
–
–
6
–
–
–
6
Write setup to clock high
t
–
–
–
6, 7
6, 8
6
WS
Chip select setup to clock high
Address hold from clock high
Data hold from clock high
t
–
–
–
CSS
t
–
–
–
AH
DH
WH
t
–
–
–
6
Write hold from clock high
Chip select hold from clock high
Clock enable setup to clock high
Clock enable hold from clock high
ADV setup to clock high
t
–
–
–
6, 7
6, 8
6
t
–
–
–
CSH
t
–
–
–
CENS
CENH
ADVS
ADVH
t
t
–
–
–
6
–
–
–
6
ADV hold from clock high
t
–
–
–
6
1 See “Notes” on page 19
4/26/04, V 1.2
Alliance Semiconductor
P. 9 of 22
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
