AS7C33256PFD32A
AS7C33256PFD36A
®
Timing waveform of read cycle
t
CH
CLK
t
ADSPS
t
ADSPH
ADSP
t
ADSCS
t
ADSCH
ADSC
t
AS
t
AH
Address
A1
t
WS
t
WH
GWE, BWE
t
CSS
t
CSH
CE0, CE2
A2
A3
LOAD NEW ADDRESS
t
CYC
t
CL
CE1
t
ADVS
t
ADVH
ADV
OE
t
HZOE
t
OH
D
OUT
(pipelined mode) t
OE
t
LZOE
D
OUT
(flow-through mode)
Q(A1)
Q(A2Ý01)
Q(A2Ý10)
Q(A2Ý11)
Q(A3)
Q(A3Ý01)
Q(A3Ý10)
Q(A3Ý11)
Q(A1)
Q(A2)
Q(A2Ý01)
t
CD
ADV INSERTS WAIT STATES
Q(A2Ý10)
Q(A2Ý11)
Q(A3)
Q(A3Ý01)
Q(A3Ý10)
t
HZC
Q(A3Ý11)
t
HZC
Note: Ý = XOR when MODE = HIGH/No Connect; Ý = ADD when MODE = LOW.
BW[a:d] is don’t care.
Key to switching waveform
Rising input
Falling input
Undefined/don’t care
5/25/01; v.0.9.1
Alliance Semiconductor
P. 7 of 11