AS7C33256PFD32A
AS7C33256PFD36A
®
AC test conditions
• Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C.
Thevenin equivalent:
• Input pulse level: GND to 3V. See Figure A.
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
+3.3V for 3.3V I/O;
+2.5V for 2.5V I/O
317
Ω
Z = 50
Ω
50
Ω
0
D
V = 1.5V
OUT
+3.0V
D
L
OUT
90%
10%
90%
10%
5 pF*
GND
for 3.3V I/O;
30 pF*
351
Ω
= V
/2
DDQ
*including scope
and jig capacitance
GND
for 2.5V I/O
Figure A: Input waveform
Figure B: Output load (A)
Figure C: Output load(B)
Notes
1
2
3
4
5
6
For test conditions, see AC Test Conditions, Figures A, B, C.
This parameter measured with output load condition in Figure C.
This parameter is sampled, but not 100% tested.
t
is less than t
; and t
is less than t at any given temperature and voltage.
HZC LZC
HZOE
LZOE
tCH measured as HIGH above VIH and tCL measured as LOW below VIL.
This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times for all rising edges of CLK when chip is enabled.
7
8
Write refers to GWE
Chip select refers to CE0
,
BWE
,
BW[a:d].
CE2
,
CE1
,
.
Package Dimensions
100-pin quad flat pack (TQFP)
TQFP
Hd
D
Min
0.05
1.35
0.22
0.09
13.90
19.90
Max
0.15
1.45
0.38
0.20
14.10
20.10
A1
A2
b
b
e
c
D
E
e
0.65 nominal
Hd
He
L
15.90
21.90
0.45
16.10
22.10
0.75
He
E
L1
α
1.00 nominal
0°
7°
Dimensions in millimeters
c
L1
L
α
A1 A2
5/25/01; v.0.9.1
Alliance Semiconductor
P. 10 of 11
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
