AS7C33256NTD32A
AS7C33256NTD36A
®
Signal descriptions
Signal
I/O Properties Description
CLK
I
I
I
CLOCK Clock. All inputs except OE, LBO, and ZZ are synchronous to this clock.
CEN
SYNC
SYNC
SYNC
Clock enable. When de-asserted high, the clock input signal is masked.
Address. Sampled when all chip enables are active and ADV/LD is asserted.
Data. Driven as output when the chip is enabled and OE is active.
A, A0, A1
DQ[a,b,c,d] I/O
CE0, CE1,
CE2
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted.
Are ignored when ADV/LD is high.
I
SYNC
Advance or Load. When sampled high, the internal burst address counter will increment in
the order defined by the LBO input value. (refer to table on page 2) When low, a new
address is loaded.
ADV/LD
R/W
I
I
SYNC
A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE
operation. Is ignored when ADV/LD is high.
SYNC
SYNC
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.
BW[a,b,c,d]
OE
I
I
ASYNC Asynchronous output enable. I/O pins are not driven when OE is inactive.
Selects Burst mode. When tied to V or left floating, device follows Interleaved Burst
DD
LBO
I
STATIC order. When driven Low, device follows linear Burst order. This signal is internally pulled
High.
ZZ
I
-
ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
NC
-
No connect. Note that pin 84 will be used for future address expansion to 16Mb density.
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to I . The
SB2
duration of SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, I
is guaranteed after the time t is met. After entering SNOOZE MODE, all inputs
ZZI
SB2
except ZZ is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed
to successfully complete. Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations
are completed. Similarly, when exiting SNOOZE MODE during t , only a DESELECT or READ cycle should be given while
PUS
the SRAM is transitioning out of SNOOZE MODE.
11/30/04, v. 2.1
Alliance Semiconductor
P. 5 of 19
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
