AS7C33256NTD32A
AS7C33256NTD36A
®
Timing characteristics for 3.3 V I/O operation
–166
–133
1
Parameter
Clock frequency
Symbol
Min Max Min Max
Unit
MHz
ns
ns
Notes
f
–
166
–
–
133
–
Max
Cycle time
t
6
7.5
–
CYC
Clock access time
t
–
3.5
3.5
–
4.0
4.0
–
CD
Output enable low to data valid
Clock high to output low Z
Data output invalid from clock high
Output enable low to output low Z
Output enable high to output High Z
Clock high to output High Z
Output enable high to invalid output
Clock high pulse width
t
–
–
ns
OE
t
0
0
ns
2,3,4
2
LZC
t
1.5
0
–
1.5
0
–
ns
OH
t
–
–
ns
2,3,4
2,3,4
2,3,4
LZOE
HZOE
t
–
3.5
3.5
–
–
4.0
4.0
–
ns
t
–
–
ns
HZC
t
0
0
ns
ns
OHOE
t
2.4
2.3
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
0.5
1.5
0.5
–
2.5
2.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
0.5
1.5
0.5
–
5
5
CH
Clock low pulse width
t
t
t
–
–
ns
CL
AS
DS
Address and control setup to clock high
Data setup to clock high
–
–
ns
6
–
–
ns
6
Write setup to clock high
t
–
–
ns
6,7
6,8
6
WS
Chip select setup to clock high
Address hold from clock high
Data hold from clock high
Write hold from clock high
Chip select hold from clock high
Clock enable setup to clock high
Clock enable hold from clock high
ADV/LD setup to clock high
ADV/LD hold from clock high
t
–
–
ns
CSS
t
–
–
ns
AH
DH
WH
t
–
–
ns
6
t
–
–
ns
6,7
6,8
6
t
–
–
ns
CSH
t
–
–
ns
CENS
CENH
ADVS
ADVH
t
t
–
–
ns
6
–
–
ns
6
t
–
–
ns
6
1 Refer to “notes” on page 16.
11/30/04, v. 2.1
Alliance Semiconductor
P. 9 of 19