AS7C33256NTD32A
AS7C33256NTD36A
®
Functional description
The AS7C33256NTD32/36A family is a high performance CMOS 8 Mbit synchronous Static Random Access Memory (SRAM) organized
as 262,144 words × 32 or 36 bits and incorporates a LATE LATE Write.
This variation of the 8Mb sychronous SRAM uses the No Turnaround Delay (NTD™) architecture, featuring an enhanced write operation
that improves bandwidth over pipelined burst devices. In a normal pipelined burst device, the write data, command, and address are all
applied to the device on the same clock edge. If a read command follows this write command, the system must wait for two 'dead' cycles for
valid data to become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or
read-modify-write operations.
NTD™ devices use the memory bus more efficiently by introducing a write latency which matches the two-cycle pipelined or one-cycle
flow-through read latency. Write data is applied two cycles after the write command and address, allowing the read pipeline to clear. With
NTD™, write and read operations can be used in any order without producing dead bus cycles.
Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 32/36 bit writes.
Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device two clock
cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; it can be tied low for
normal operations. Outputs go to a high impedance state when the device is de-selected by any of the three chip enable inputs. In pipelined
mode, a two cycle deselect latency allows pending read or write operations to be completed.
Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip select,
R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device operations,
including burst, can be stalled using the CEN=1, the clock enable input.
The AS7C33256NTD36A and AS7C33256NTD32A operate with a 3.3V ± 5% power supply for the device core (VDD). DQ circuits use a
separate power supply (VDDQ) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin 14×20 mm TQFP package
Capacitance
Parameter
Symbol
Test conditions
V = 0V
Min
Max
Unit
pF
*
Input capacitance
I/O capacitance
C
-
-
5
7
IN
in
*
C
V = V = 0V
pF
I/O
in
out
*
Guaranteed not tested
TQFP thermal resistance
Description
Conditions
Symbol
Typical
40
Units
°C/W
°C/W
1–layer
4–layer
θJA
θJA
Thermal resistance
(junction to ambient)1
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51
22
Thermal resistance
(junction to top of case)1
θJC
8
°C/W
1 This parameter is sampled
11/30/04, v. 2.1
Alliance Semiconductor
P. 4 of 19
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
