AS7C331MNTD32A
AS7C331MNTD36A
®
TAP timing diagram
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
THTH
THTL
TLTH
Test Mode Select
(TMS)
t
t
MVTH THMX
Test Data-In
(TDI)
t
TLOV
t
t
DVTH
THDX
t
TLOX
Test Data-Out
(TDO)
Undefined
Don’t care
TAP AC electrical characteristics
o
o
For notes 1 and 2, +10 C ≤ T ≤ +110 C and +2.4V ≤ V ≤ +2.6V.
J
DD
Description
Symbol
Min Max Units
Clock
Clock cycle time
Clock frequency
Clock high time
Clock low time
Output Times
tTHTH
fTF
tTHTL
tTLTH
50
ns
MHz
ns
20
10
20
20
ns
TCK low to TDO unknown
TCK low to TDO valid
TDI valid to TCK high
TCK high to TDI invalid
Setup Times
tTLOX
tTLOV
tDVTH
tTHDX
0
ns
ns
ns
ns
5
5
TMS setup
tMVTH
tCS1
5
5
ns
ns
Capture setup
Hold Times
TMS hold
tTHMX
tCH1
5
5
ns
ns
Capture hold
1 tCS and tCH refer to the setup and hold time requirements of latching
data from the boundary scan register.
2 Test conditions are specified using the load in the figure TAP AC output
load equivalent.
TAP AC test conditions
TAP AC output load equivalent
VDDQ/2
Input pulse levels. . . . . . . . . . . . . . . Vss to V
DD
Input rise and fall times. . . . . . . . . . . . . . . 1 ns
50Ω
Input timing reference levels. . . . . . . . . . V
Output reference levels . . . . . . . . . . . . . . V
Test load termination supply voltage. . . . V
/2
DDQ
DDQ
DDQ
TDO
/2
/2
20p
Z =50
O
4/26/04, V 1.2
Alliance Semiconductor
P. 13 of 22
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
