AS7C331MNTD32A
AS7C331MNTD36A
®
TAP instruction set
Eight different instructions are possible with the 3-bit instruction register. All combinations are listed in the Instruction Codes
table. One of these instructions is reserved and should not be used.
Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI
and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins/balls. To
execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s.
EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1.
The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two
instructions, unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state.
IDCODE
The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test
logic reset state. The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the identification register. It
also places the identification register between the TDI and TDO pins/balls and allows the IDCODE to be shifted out of the
device when the TAP controller enters the Shift-DR state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins/balls when the
TAP controller is in a Shift-DR state. It also places all SRAM outputs into a high-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE/PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAM’s input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet.Because
the RAM clock is independent from the TAP clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be accepted. RAM input signals must be stabilized for long enough to meet the
TAP’s input data capture set-up plus hold time (tCS plus tCH). The RAM’s clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
BYPASS
The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected
together on a board. When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR
state, the bypass register is placed between TDI and TDO.
RESERVED
Do not use a reserved instruction. These instructions are not implemented but are reserved for future use.
4/26/04, V 1.2
Alliance Semiconductor
P. 12 of 22
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
