AS7C331MNTD32A
AS7C331MNTD36A
®
IEEE 1149.1 serial boundary scan (JTAG)
The SRAM incorporates a serial boundary scan test access port (TAP). The port operates in accordance with IEEE Standard
1149.1-1990. The SRAM contains a TAP controller, instruction register, boundary scan register, bypass register, and ID
register.
Disabling the JTAG feature
If the JTAG function is not being implemented, TCK should be grounded to avoid mid-level input. At power-up, the device
will come up in a reset state which will not interfere with the operation of the device.
TAP controller state diagram
TAP controller block diagram
TEST-LOGIC
RESET
1
0
0
1
SELECT
DR-SCAN
1
1
SELECT
IR-SCAN
RUN-TEST/
IDLE
Bypass Register
0
Selection
Circuitry
Selection
Circuitry
2
1 0
0
0
Instruction Register
TDI
TDO
1
1
.
. .
2
3130 29
1 0
CAPTURE-DR
0
CAPTURE-IR
0
Identification Register
.
. . . .
2
x
1 0
1
Boundary Scan Register
SHIFT-DR
1
0
SHIFT-IR
1
0
1
1
EXIT1-IR
0
EXIT1-DR
0
TCK
TMS
TAP Controller
PAUSE-IR
1
PAUSE-DR
1
0
0
1
x = 75
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-IR
UPDATE-DR
1
0
1
0
Note: The 0 or 1 next to each state represents the value of TMS at the rising edge of TCK.
Test access port (TAP)
Test clock (TCK)
The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test mode select (TMS)
The TAP controller receives commands from TMS input. It is sampled on the rising edge of TCK. You can leave this pin/ball
unconnected if the TAP is not used. The pin/ball is pulled up internally, resulting in a logic high level.
Test data-in (TDI)
The TDI pin/ball serially inputs information into the registers and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on
4/26/04, V 1.2
Alliance Semiconductor
P. 10 of 22
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