ꢊꢐꢗꢀ##"$%&ꢞ"(ꢊ
&
Functional description
The AS7C331MNTD18A family is a high performance CMOS 16 Mbit synchronous Static Random Access Memory (SRAM) organized as
1,048,576 words × 18 bits and incorporates a LATE LATE Write.
™
This variation of the 16Mb+ synchronous SRAM uses the No Turnaround Delay (NTD ) architecture, featuring an enhanced write operation
that improves bandwidth over pipeline burst devices. In a normal pipeline burst device, the write data, command, and address are all applied to
the device on the same clock edge. If a read command follows this write command, the system must wait for two 'dead' cycles for valid data to
become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or read-modify-write
operations.
™
NTD devices use the memory bus more efficiently by introducing a write 'latency' which matches the two (one) cycle pipeline
(flowthrough) read latency. Write data is applied two cycles after the write command and address, allowing the read pipeline to clear. With
™
NTD , write and read operations can be used in any order without producing dead bus cycles.
Assert R/ W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 18 bit writes. Write
enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device two clock cycles
later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; it can be tied low for normal
operations. Outputs go to a high impedance state when the device is de-selected by any of the three chip enable inputs. In pipeline mode, a two
cycle deselect latency allows pending read or write operations to be completed.
Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip select, R/ W pins
are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device operations, including burst, can
be stalled using the CEN=1, the clock enable input.
The AS7C331MNTD18A operates with a 3.3V ± 5% power supply for the device core (V ). DQ circuits use a separate power supply (V
)
DD
DDQ
that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin TQFP package and 165 BGA Ball Grid Array package.
Capacitance
Parameter
Symbol
Signals
Address and control pins
I/ O pins
Test conditions
V = 0V
Max
5
Unit
pF
Input capacitance
I/ O capacitance
C
IN
in
C
V = Vout = 0V
7
pF
I/ O
in
Burst order
Interleaved burst order LBO = 1
A1A0 A1A0 A1A0 A1A0
Linear burst order LBO = 0
A1A0 A1A0 A1A0 A1A0
Starting address
First increment
0 0
0 1
0 1
0 0
1 1
1 0
1 0
1 1
0 0
0 1
1 1
1 0
0 1
0 0
Starting Address
First increment
0 0
0 1
0 1
1 0
1 1
0 0
1 0
1 1
0 0
0 1
1 1
0 0
0 1
1 0
Second increment 1 0
Third increment 1 1
Second increment 1 0
Third increment 1 1
ꢉꢗꢘꢙꢙꢘꢚꢙꢛꢉꢖꢔꢚꢔꢜꢔꢗꢊꢒꢖꢌꢍꢎꢏꢝꢍ ꢁ
ꢀꢋꢋꢌꢍꢎꢏꢐꢑꢁꢐꢒꢌꢏꢓꢎꢔꢕꢏꢖꢓꢗ
!ꢔꢉ#ꢉꢁ ꢉ"ꢜ
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
