ꢊꢐꢗꢀ##"$%&ꢞ"(ꢊ
&
Timing characteristics over operating range
250
200
166
100
Parameter
Sym
FMAX
tCYC
Unit Notes1
Min
-
Max
Min
-
Max
Min
-
Max
Min
-
Max
100
-
Clock frequency
250
-
200
-
166
-
MHz
ns
Cycle time (pipelined mode)
Cycle time (flow-through mode)
Clock access time (pipelined mode)
4
5
6
10
10
-
tCYCF 7.5
-
7.5
-
-
8.5
-
-
-
ns
tCD
-
2.6
3.0
3.4
4.0
ns
Clock access time (flow-through
mode)
tCDF
-
6.5
-
6.5
-
7.5
-
8.5
ns
Output enable Low to data valid
Clock High to output Low Z
tOE
tLZC
tOH
-
0
2.6
-
-
0
3.0
-
-
0
3.4
-
-
0
4.0
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
2, 3, 4
Data output invalid from clock High
Output enable Low to output Low Z
1.5
0
-
1.5
0
-
1.5
0
-
1.5
0
-
4
tLZOE
-
-
-
-
2, 3, 4
Output enable High to output High Z tHZOE
-
3.0
3.0
1.5
-
-
3.0
3.0
1.5
-
-
3.0
3.0
1.5
-
-
4.0
4.0
2.5
-
2, 3, 4
Clock High to output High Z
Clock High to output High Z
Clock High pulse width
tHZC
tHZCN
tCH
-
-
-
-
2, 3, 4
-
-
-
-
5
8
8
1.5
1.5
1.5
1.5
1.8
1.8
3.0
3.0
Clock Low pulse width
tCL
-
-
-
-
Address and Control setup to clock
High
tAS
1.2
-
1.5
-
1.5
-
1.5
-
ns
9
Data setup to clock High
tDS
tWS
tCSS
tAH
1.2
1.2
1.2
0.3
0.3
0.3
0.3
-
-
-
-
-
-
-
-
-
-
-
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
0.5
1.5
0.5
-
-
-
-
-
-
-
-
-
-
-
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
0.5
1.5
0.5
-
-
-
-
-
-
-
-
-
-
-
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
0.5
1.5
0.5
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9
9
9
9
9
9
9
9
9
9
9
Write setup to clock High
Chip select setup to clock High
Address hold from clock High
Data hold from clock High
Write hold from clock High
Chip select hold from clock High
Clock enable setup to clock high
Clock enable hold from clock high
ADV setup to clock high
tDH
tWH
tCSH
tCENS 1.2
tCENH 0.3
tADVS 1.2
tADVH 0.3
ADV hold from clock high
1 See “Notes” on page 17
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ISSI [ INTEGRATED SILICON SOLUTION, INC ]
