June 2002
Advance Information
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TM
Features
• Organization: 1,048,576 words × 18 bits
• NTD
™1
architecture for efficient bus operation
• Fast clock speeds to 250 MHz in LVTTL/LVCMOS
• Fast clock to data access: 2.6/3/3.4/4 ns
• Fast OE access time: 2.6/3/3.4/4 ns
• Fully synchronous operation
• “Flow-through” or “pipelined” mode
• Asynchronous output enable control
1. NTD
TM
is a trademark of Alliance Semiconductor Corporation.
• Available in 100-pin TQFP and 165-ball BGA package
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V
DDQ
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
Logic block diagram
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Selection guide
-250
Minimum cycle time
Maximum pipelined clock frequency
Maximum pipelined clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
Y $GYDQFH,QIR
-200
5
200
3.0
400
160
30
-166
6
166
3.4
350
120
30
-100
10
100
4.0
230
70
30
Units
ns
MHz
ns
mA
mA
mA
3 RI
4
250
2.6
400
160
30
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ISSI [ INTEGRATED SILICON SOLUTION, INC ]
