AS7C25512PFS32A
AS7C25512PFS36A
®
AC test conditions
• Output load: For t , t
, t
, t , see Figure C. For all others, see Figure B.
LZC LZOE HZOE HZC
• Input pulse level: GND to 3V. See Figure A.
Thevenin equivalent:
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
+2.5V
319Ω/1667Ω
Z = 50
Ω
50
Ω
0
D
OUT
+3.0V
D
V = V / 2
L DDQ
OUT
5 pF*
90%
10%
90%
10%
353Ω/1538Ω
30 pF*
GND
*including scope
and jig capacitance
GND
Figure C: Output load(B)
Figure A: Input waveform
Figure B: Output load (A)
Notes
1
2
3
4
5
6
For test conditions, see “AC test conditions”, Figures A, B, and C.
This parameter is measured with output load condition in Figure C.
This parameter is sampled but not 100% tested.
t
t
is less than t
, and t
LZOE
is less than t at any given temperature and voltage.
HZC LZC
HZOE
CH
is measured as high if above VIH, and t is measured as low if below VIL.
CL
This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet
the setup and hold times for all rising edges of CLK when chip is enabled.
Write refers to GWE, BWE, and BW[a:d].
7
8
Chip select refers to CE0, CE1, and CE2.
12/ 2/ 02, v. 0.9.1
Alliance Semiconductor
19 of 21
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
