$6&017'$
Synchronous truth table
CE0
H
X
X
L
L
X
X
CE1
X
L
X
H
H
X
X
CE2
X
X
H
L
L
X
X
ADV/LD
L
L
L
L
L
H
X
R/W BW[a,b]
X
X
X
H
L
X
X
X
X
X
X
L
X
1
X
OE
X
X
X
X
X
X
X
CEN
L
L
L
L
L
L
H
Address source
NA
NA
NA
External
External
Burst counter
Stall
CLK
L to H
L to H
L to H
L to H
L to H
L to H
L to H
Operation
Deselect, high-Z
Deselect, high-Z
Deselect, high-Z
Begin read
Begin write
Burst
2
Inhibit the CLK
1 Should be low for burst write unless specific bytes need to be inhibited
2 Refer to state diagram below.
Key: X = don’t care, L = low, H = high
State diagram for NTD SRAM
5HDG
5HDG
5H
%XUVW
5HDG
%XUVW
5HDG
'VHO
%XUVW
'V
HO
DG
'VHO
'VHO
%XUVW
5
HD
:
ULW
H
5HDG
:ULWH
:ULWH
Recommended operating conditions
Parameter
Supply voltage
Address and
control pins
Input voltages
I/O pins
Ambient operating temperature
Symbol
V
DD
, V
DDQ
GND
V
IH
V
IL
V
IH
V
IL
T
A
Min
2.35
0.0
2.0
–0.5
1
2.0
-0.5
1
0
Nominal
2.5
0.0
–
–
–
–
–
Max
2.65
0.0
V
DD
+ 0.3
0.4
V
DDQ
+ 0.3
0.4
70
Unit
V
V
V
°C
:ULWH
G
LWH
:U
%XUVW
:ULWH
'V
HO
'VHO
%XUVW
:ULWH
%XUVW
1 V
IL
min = –2.0V for pulse width less than 0.2 x t
RC
.
Y
$OOLDQFH 6HPLFRQGXFWRU
3 RI
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
