AS7C251MNTD18A-225TQI 参数 Datasheet PDF下载

$6&017'$

Š

Functional description

The AS7C251MNTD18A family is a high performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) organized as

1,048,576 words × 18 bits and incorporates a LATE LATE Write.

This variation of the 16Mb+ synchronous SRAM uses the No Turnaround Delay (NTD

™

) architecture, featuring an enhanced write operation

that improves bandwidth over pipelined burst devices. In a normal pipelined burst device, the write data, command, and address are all applied

to the device on the same clock edge. If a read command follows this write command, the system must wait for two 'dead' cycles for valid data

to become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or read-modify-

write operations.

NTD

™

devices use the memory bus more efficiently by introducing a write latency which matches the two-cycle pipelined or one-cycle flow-

through read latency. Write data is applied two cycles after the write command and address, allowing the read pipeline to clear. With NTD

™

,

write and read operations can be used in any order without producing dead bus cycles.

Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 18 bit writes. Write

enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device two clock cycles

later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; it can be tied low for normal

operations. Outputs go to a high impedance state when the device is de-selected by any of the three chip enable inputs. In pipelined mode, a

two cycle deselect latency allows pending read or write operations to be completed.

Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip select, R/W pins

are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device operations, including burst, can

be stalled using the CEN=1, the clock enable input.

The AS7C251MNTD18A operates with a 2.5V ± 5% power supply for the device core (V

DD

). These devices are available in a 100-pin TQFP

package and 165 BGA Ball Grid Array package.

Capacitance

Parameter

Input capacitance

I/O capacitance

Symbol

C

IN

C

I/O

I/O pins

Signals

Address and control pins

Test conditions

V

in

= 0V

V

in

= V

out

= 0V

Max

5

7

Unit

pF

pF

Burst order

Interleaved burst order LBO = 1

A1A0

Starting address

First increment

Second increment

Third increment

0 0

0 1

1 0

1 1

A1A0

0 1

0 0

1 1

1 0

A1A0

1 0

1 1

0 0

0 1

A1A0

1 1

1 0

0 1

0 0

Starting Address

First increment

Second increment

Third increment

Linear burst order LBO = 0

A1A0

0 0

0 1

1 0

1 1

A1A0

0 1

1 0

1 1

0 0

A1A0

1 0

1 1

0 0

0 1

A1A0

1 1

0 0

0 1

1 0

 Y 

$OOLDQFH 6HPLFRQGXFWRU

3  RI