IRLML2803
160
140
120
100
C, Capacitance (pF)
C
iss
C
oss
80
60
40
20
0
1
10
100
V
GS
, Gate-to-Source Voltage (V)
V
GS
= 0V,
f = 1MHz
C
iss
= C
gs
+ C
gd
, C
ds
SHORTED
C
rss
= C
gd
C
oss
= C
ds
+ C
gd
20
I
D
= 0.91A
V
DS
= 24V
V
DS
= 15V
16
12
8
C
rss
4
A
0
0.0
FOR TEST CIRCUIT
SEE FIGURE 9
1.0
2.0
3.0
4.0
5.0
A
V
DS
, Drain-to-Source Voltage (V)
Q
G
, Total Gate Charge (nC)
Fig 5.
Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6.
Typical Gate Charge Vs.
Gate-to-Source Voltage
10
100
I
SD
, Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
T
J
= 150°C
I
D
, Drain Current (A)
10
10µs
1
T
J
= 25°C
100µs
1
1ms
0.1
0.4
0.6
0.8
1.0
V
GS
= 0V
1.2
A
0.1
1
T
A
= 25°C
T
J
= 150°C
Single Pulse
10
10ms
A
100
1.4
V
SD
, Source-to-Drain Voltage (V)
V
DS
, Drain-to-Source Voltage (V)
Fig 7.
Typical Source-Drain Diode
Forward Voltage
Fig 8.
Maximum Safe Operating Area