X9428
A.C. TEST CONDITIONS
Input
pulse levels
Input rise and fall times
Input and output timing level
V
CC
x 0.1 to V
CC
x 0.9
10ns
V
CC
x 0.5
R
H
C
H
10pF
5V
1533Ω
SDA Output
100pF
100pF
2.7V
C
W
25pF
R
W
Circuit #3 SPICE Macro Model
R
TOTAL
C
L
10pF
R
L
EQUIVALENT A.C. LOAD CIRCUIT
AC TIMING
(over recommended operating conditions)
Symbol
f
SCL
t
CYC
t
HIGH
t
LOW
t
SU:STA
t
HD:STA
t
SU:STO
t
SU:DAT
t
HD:DAT
t
R
t
F
t
AA
t
DH
T
I
t
BUF
t
SU:WPA
t
HD:WPA
Clock frequency
Clock cycle time
Clock high time
Clock low time
Start setup time
Start hold time
Stop setup time
SDA data input setup time
SDA data input hold time
SCL and SDA rise time
SCL and SDA fall time
SCL low to SDA data output valid time
SDA data output hold time
Noise suppression time constant at SCL and SDA inputs
Bus free time (prior to any transmission)
WP, A0, A1, A2 and A3 setup time
WP, A0, A1, A2 and A3 hold time
50
50
1300
0
0
Parameter
Min.
100
2500
600
1300
600
600
600
100
30
Max.
400
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
300
300
900
ns
ns
ns
ns
ns
ns
ns
ns
15
FN8197.1
April 26, 2006
INTERSIL [ INTERSIL CORPORATION ]
